Datasheet

Errata
36 Specification Update
AR44. SYSCALL Immediately after Changing EFLAGS.TF May Not Behave
According to the New EFLAGS.TF
Problem: If a SYSCALL instruction follows immediately after EFLAGS.TF was updated and
IA32_FMASK.TF (bit 8) is cleared, then under certain circumstances SYSCALL may
behave according to the previous EFLAGS.TF.
Implication: When the problem occurs, SYSCALL may generate an unexpected debug exception, or
may skip an expected debug exception.
Workaround: Mask EFLAGS.TF by setting IA32_FMASK.TF (bit 8).
Status: For the steppings affected, see the Summary Tables of Changes.
AR45. VM Bit is Cleared on Second Fault Handled by Task Switch from
Virtual- 8086 (VM86)
Problem: Following a task switch to any fault handler that was initiated while the processor was
in VM86 mode, if there is an additional fault while servicing the original task switch
then the VM bit will be incorrectly cleared in EFLAGS, data segments will not be
pushed and the processor will not return to the correct mode upon completion of the
second fault handler via IRET.
Implication: When the OS recovers from the second fault handler, the processor will no longer be
in VM86 mode. Normally, operating systems should prevent interrupt task switches
from faulting, thus the scenario should not occur under normal circumstances.
Workaround: None Identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AR46. IA32_FMASK Is Reset during an INIT
Problem: IA32_FMASK MSR (0xC0000084) is reset during INIT.
Implication: If an INIT takes place after IA32_FMASK is programmed, the processor will overwrite
the value back to the default value.
Workaround: Operating system software should initialize IA32_FMASK after INIT.
Status: For the steppings affected, see the Summary Tables of Changes.