Datasheet

Errata
Specification Update 35
AR41. Concurrent Multi-processor Writes to Non-dirty Page May Result in
Unpredictable Behavior
Problem: When a logical processor writes to a non-dirty page, and another logical-processor
either writes to the same non-dirty page or explicitly sets the dirty bit in the
corresponding page table entry, complex interaction with internal processor activity
may cause unpredictable system behavior.
Implication: This erratum may result in unpredictable system behavior and hang.
Workaround: It is possible for BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
AR42. Performance Monitor IDLE_DURING_DIV (18h) Count May Not Be
Accurate
Problem: Performance monitoring events that count the number of cycles the divider is busy
and no other execution unit operation or load operation is in progress may not be
accurate.
Implication: The counter may reflect a value higher or lower than the actual number of events.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AR43. Values for LBR/BTS/BTM Will Be Incorrect after an Exit from SMM
Problem: After a return from SMM (System Management Mode), the CPU will incorrectly update
the LBR (Last Branch Record) and the BTS (Branch Trace Store), hence rendering
their data invalid. The corresponding data if sent out as a BTM on the system bus will
also be incorrect.
Note: This issue would only occur when one of the 3 above mentioned debug support
facilities are used.
Implication: The value of the LBR, BTS, and BTM immediately after an RSM operation should not
be used.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.