Datasheet

Summary Tables of Changes
16 Specification Update
Stepping Stepping
Number
A1 E1
Plans ERRATA
AR86
X X
No Fix
Performance Monitoring Event SIMD_UOP_TYPE_EXEC.MUL is
Counted Incorrectly for PMULUDQ Instruction
AR87
X X
No Fix
Storage of PEBS Record Delayed Following Execution of MOV SS or
STI
AR88
X X
No Fix Updating Code Page Directory Attributes without TLB Invalidation May
Result in Improper Handling of Code #PF
AR89
X X
Plan Fix Performance Monitoring Event CPU_CLK_UNHALTED.REF May Not
Count Clock Cycles According to the Processors Operating Frequency
AR90 X X Plan Fix Store Ordering May Be Incorrect between WC and WP Memory Types
AR91
X
Fixed Performance Monitoring Event BR_INST_RETIRED May Count CPUID
Instructions as Branches
AR92 X X No Fix Performance Monitoring Event MISALIGN_MEM_REF May over Count
AR93
X X
No Fix A REP STOS/MOVS to a MONITOR/MWAIT Address Range May
Prevent Triggering of the Monitoring Hardware
AR94 X Fixed
False Level One Data Cache Parity Machine-Check Exceptions May Be
Signaled
AR95 X X No Fix
A Memory Access May Get a Wrong Memory Type Following a #GP
due to WRMSR to an MTRR Mask
AR96 X X No Fix
PMI While LBR Freeze Enabled May Result in Old/Out-of-date LBR
Information
AR97 x No Fix BIST Failure after Reset
AR99 X X No Fix
Instruction Fetch May Cause a Livelock during Snoops of the L1 Data
Cache.
AR100 X X No Fix
Use of Memory Aliasing with Inconsistent Memory Type may Cause a
System Hang or a Machine Check Exception
AR101 X X No Fix
A WB Store Following a REP STOS/MOVS or FXSAVE May Lead to
Memory-Ordering Violations
AR102 X X No Fix
Using Memory Type Aliasing with Cacheable and WC Memory Types
May Lead to Memory Ordering Violations
AR103 X X No Fix
RSM Instruction Execution under Certain Conditions May Cause
Processor Hang or Unexpected Instruction Execution Results
AR104 X X Plan Fix NMIs May Not Be Blocked by a VM-Entry Failure
AR105 X X No Fix
Benign Exception after a Double Fault May Not Cause a Triple Fault
Shutdown