Datasheet
Summary Tables of Changes
Specification Update 15
Stepping
Stepping
Number
A1 E1
Plans ERRATA
AR64 X X No Fix PMI May Be Delayed to Next PEBS Event
AR65
X
Fixed PEBS Buffer Overflow Status Will Not Be Indicated Unless
IA32_DEBUGCTL[12] Is Set
AR66 X X No Fix The BS Flag in DR6 May Be Set for Non-Single-Step #DB Exception
AR67 X X No Fix An Asynchronous MCE during a Far Transfer May Corrupt ESP
AR68 X X No Fix B0-B3 Bits in DR6 May Not Be Properly Cleared after Code Breakpoint
AR69
X X
No Fix BTM/BTS Branch-From Instruction Address May Be Incorrect for
Software Interrupts
AR70
X
Fixed REP Store Instructions in a Specific Situation May Cause the Processor
to Hang
AR71
X X
No Fix Performance Monitor SSE Retired Instructions May Return Incorrect
Values
AR72
X X
No Fix Performance Monitoring Events for L1 and L2 Miss May Not Be
Accurate
AR73
X X
No Fix Store to WT Memory Data May Be Seen in Wrong Order by Two
Subsequent Loads
AR74
X
No Fix A MOV Instruction from CR8 Register with 16 Bit Operand Size Will
Leave Bits 63:16 of the Destination Register Unmodified
AR75
X
Fixed Debug Register May Contain Incorrect Information on a MOVSS or
POPSS Instruction followed by SYSRET
AR76
X X
No Fix Single Step Interrupts with Floating Point Exception Pending May Be
Mishandled
AR77
X X
No Fix Fault on ENTER Instruction May Result in Unexpected Values on Stack
Frame
AR78
X X
No Fix Unaligned Accesses to Paging Structures May Cause the Processor to
Hang
AR79
X X
No Fix INVLPG Operation for Large (2M/4M) Pages May Be Incomplete under
Certain Conditions
AR80
X X
No Fix Page Access Bit May Be Set Prior to Signaling a Code Segment Limit
Fault
AR81
X
X Plan Fix
Update of Attribute Bits on Page Directories without Immediate TLB
Shootdown May Cause Unexpected Processor Behavior
AR82
X
Fixed Invalid Instructions May Lead to Unexpected Behavior
AR83
X X
No Fix
EFLAGS, CR0, CR4 and the EXF4 Signal May Be Incorrect after
Shutdown
AR84
X
Fixed
Performance Monitoring Counter MACRO_INSTS.DECODED May Not
Count Some Decoded Instructions
AR85
X X
Plan Fix
The Stack May Be Incorrect as a Result of VIP/VIF Check on SYSEXIT
and SYSRET