Datasheet
Summary Tables of Changes
Specification Update 13
Stepping
Stepping
Number
A1 E1
Plans ERRATA
AR21
X
Fixed Sequential Code Fetch to Non-canonical Address May have
Nondeterministic Results
AR22
X X
No Fix REP MOVS/STOS Executing with Fast Strings Enabled and Crossing
Page Boundaries with Inconsistent Memory Types May Use an
Incorrect Data Size or Lead to Memory-Ordering Violations.
AR23
X X
No Fix Some Bus Performance Monitoring Events May Not Count Local
Events under Certain Conditions
AR24
X X
No Fix Premature Execution of a Load Operation Prior to Exception Handler
Invocation
AR25
X X
No Fix General Protection (#GP) Fault May Not Be Signaled on Data Segment
Limit Violation above 4-G Limit
AR26 X X No Fix EIP May Be Incorrect after Shutdown in IA-32e Mode
AR27
X X
No Fix #GP Fault Is Not Generated on Writing IA32_MISC_ENABLE [34]
When Execute Disable Is Not supported
AR28
X
Fixed (E)CX May Get Incorrectly Updated Fast String REP MOVS or Fast
String REP STOS with Large Data Structures
AR29
X
Fixed Performance Monitoring Events for Retired Loads (CBH) and
Instructions Retired (C0H) May Not Be Accurate
AR30
X X
No Fix Upper 32 bits of 'From' Address Reported through BTMs or BTSs May
Be Incorrect
AR31
X
Fixed Unsynchronized Cross-Modifying Code Operations Can Cause
unexpected Instruction Execution Results
AR32
X X
No Fix MSRs Actual Frequency Clock Count (IA32_APERF) or Maximum
Frequency Clock Count (IA32_MPERF) May Contain Incorrect Data
after a Machine Check Exception (MCE)
AR33
X X
No Fix Incorrect Address Computed for Last Byte of FXSAVE/FXRSTOR
Image Leads to Partial Memory Update
AR34 X X No Fix Split Locked Stores May Not Trigger the Monitoring Hardware
AR35
X
Fixed REP CMPS/SCAS Operations May Terminate Early in 64-bit Mode
When RCX >= 0X100000000
AR36
X
Fixed FXSAVE/FXRSTOR Instructions which Store to the End of the Segment
and Cause a Wrap to a Misaligned Base Address (Alignment <=
0x10h) May Cause FPU Instruction or Operand Pointer Corruption
AR37
X
Fixed Cache Data Access Request from One Core Hitting a Modified Line in
the L1 Data Cache of the Other Core May Cause Unpredictable
System Behavior
AR38
X
Fixed PREFETCHh Instruction Execution under Some Conditions May Lead to
Processor Livelock
AR39
X
Fixed PREFETCHh Instructions May Not Be Executed when Alignment Check
(AC) Is Enabled
AR40
X
Fixed Upper 32 Bits of the FPU Data (Operand) Pointer in the FXSAVE
Memory Image May Be Unexpectedly All 1's after FXSAVE