Intel® Core™2 Duo Mobile Processor, Intel® Core™2 Solo Mobile Processor and Intel® Core™2 Extreme Mobile Processor on 45-nm Process Datasheet For platforms based on Mobile Intel® 4 Series Express Chipset Family March 2009 Document Number: 320120-004
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Contents 1 Introduction .............................................................................................................. 7 1.1 Terminology ....................................................................................................... 8 1.2 References ......................................................................................................... 9 2 Low Power Features ................................................................................................ 11 2.
5.2 5.3 5.1.3 Digital Thermal Sensor .......................................................................... 111 Out of Specification Detection............................................................................ 112 PROCHOT# Signal Pin ...................................................................................... 112 Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Core Low-Power States .......................................................................................
16 17 18 19 20 21 22 23 24 25 26 27 28 Pin Name Listing ...................................................................................................... 61 Pin # Listing............................................................................................................ 72 Intel Core 2 Duo Mobile Processor in SFF Package Listing by Ball Name ........................... 84 Signal Description ....................................................................................................
Revision History Document Number Revision Number 320120 -001 Description Initial Release Date July 2008 • Chapter Update — Chapter 1: Added introduction to the Intel Core 2 Duo Processor in SFF Package — Section 4.
Introduction 1 Introduction The Intel® Core™2 Duo mobile processor, Intel® Core™2 Duo mobile processor lowvoltage (LV), ultra low-voltage (ULV) in small form factor (SFF) package and Intel® Core™2 Extreme mobile are high-performance, low-power mobile processor based on the Intel Core microarchitecture for Intel® Centrino® 2 processor technology.
Introduction • Digital thermal sensor (DTS) • Intel® 64 architecture • Supports enhanced Intel® Virtualization Technology • Enhanced Intel® Dynamic Acceleration Technology and Enhanced Multi-Threaded Thermal Management (EMTTM) • Supports PSI2 functionality • SV processor offered in Micro-FCPGA and Micro-FCBGA packaging technologies • Processor in POP, LV and ULV are offered in Micro-FCBGA packaging technologies only • Execute Disable Bit support for enhanced security • Intel® Deep Power Down low-power stat
Introduction Term 1.2 Definition Execute Disable Bit The Execute Disable bit allows memory to be marked as executable or nonexecutable, when combined with a supporting operating system. If code attempts to run in non-executable memory the processor raises an error to the operating system. This feature can prevent some classes of viruses or worms that exploit buffer overrun vulnerabilities and can thus help improve the overall security of the system.
Introduction Document Number Document Volume 2B: Instruction Set Reference, N-Z 253667 Volume 3A: System Programming Guide 253668 Volume 3B: System Programming Guide 253669 NOTE: Contact your Intel representative for the latest revision of this document.
Low Power Features 2 Low Power Features 2.1 Clock Control and Low-Power States The processor supports low-power states both at the individual core level and the package level for optimal power management. A core may independently enter the C1/AutoHALT, C1/MWAIT, C2, C3, C4, Intel® Enhanced Deeper Sleep and Intel® Deep Power Down Technology low-power states.
Low Power Features Figure 1.
Low Power Features Figure 2. Package Low-Power States SLP# asserted STPCLK# asserted DPSLP# asserted Stop Grant Normal Sleep STPCLK# deasserted DPRSTP# asserted Deep Sleep SLP# deasserted DPSLP# deasserted Deeper Sleep† DPRSTP# deasserted Snoop Snoop serviced occurs Stop Grant Snoop † — Deeper Sleep includes the Deeper Sleep state, Deep C4 sub-state, and C6 Table 1.
Low Power Features The system can generate a STPCLK# while the processor is in the AutoHALT Powerdown state. When the system deasserts the STPCLK# interrupt, the processor will return execution to the HALT state. While in AutoHALT Powerdown state, the dual-core processor will process bus snoops and snoops from the other core. The processor core will enter a snoopable sub-state (not shown in Figure 1) to process the snoop and then return to the AutoHALT Powerdown state. 2.1.1.
Low Power Features 2.1.1.7 Core Deep Power Down Technology (Code Name C6) State Deep Power Down Technology state is a new, power-saving state which is being implemented on the processor. In Deep Power Down Technology the processor saves its entire architectural state onto an on-die SRAM hence allowing it to lower its main core voltage to any value, even as low as 0-V.
Low Power Features 2.1.2.3 Stop-Grant Snoop State The processor responds to snoop or interrupt transactions on the FSB while in StopGrant state by entering the Stop-Grant Snoop state. The processor will stay in this state until the snoop on the FSB has been serviced (whether by the processor or another agent on the FSB) or the interrupt has been latched. The processor returns to the Stop-Grant state once the snoop has been serviced or the interrupt has been latched. 2.1.2.
Low Power Features state, it will not respond to interrupts or snoop transactions. Any transition on an input signal before the processor has returned to Stop-Grant state will result in unpredictable behavior. 2.1.2.6 Deeper Sleep State The Deeper Sleep state is similar to the Deep Sleep state but further reduces core voltage levels. One of the potential lower core voltage levels is achieved by entering the base Deeper Sleep state.
Low Power Features 2.1.2.6.3 Dynamic Cache Sizing Dynamic Cache Sizing allows the processor to flush and disable a programmable number of L2 cache ways upon each Deeper Sleep entry under the following conditions: • The second core is already in C4 and Intel Enhanced Deeper Sleep state or Deep Power Down Technology state (C6) is enabled (as specified in Section 2.1.1.6). • The C0 timer that tracks continuous residency in the Normal package state has not expired.
Low Power Features 2.2 Enhanced Intel SpeedStep® Technology The processor features Enhanced Intel SpeedStep Technology. Following are the key features of Enhanced Intel SpeedStep Technology: • Multiple voltage and frequency operating points provide optimal performance at the lowest power.
Low Power Features 2.3 Extended Low-Power States Extended low-power states (CXE) optimize for power by forcibly reducing the performance state of the processor when it enters a package low-power state. Instead of directly transitioning into the package low-power state, the enhanced package lowpower state first reduces the performance state of the processor by performing an Enhanced Intel SpeedStep Technology transition down to the lowest operating point.
Low Power Features 2.4 FSB Low Power Enhancements The processor incorporates FSB low power enhancements: • Dynamic FSB Power Down • BPRI# control for address and control input buffers • Dynamic Bus Parking • Dynamic On-Die Termination disabling • Low VCCP (I/O termination voltage) • Dynamic FSB frequency switching The processor incorporates the DPWR# signal that controls the data bus input buffers on the processor.
Low Power Features Figure 3. Dynamic FSB Frequency Switching Protocol NOTES: 1. All common clock signals will be active for two BCLKs instead of one (e.g., ADS#, HIT#). 2. The double-pumped signal strobes will have only one transition per BCLK when active, instead of two. 3. The quad-pumped signal strobes will have only two transitions per BCLK when active, instead of four. 4. Same setup and hold times apply, but relative to every second rising BCLK. 5.
Low Power Features When in Intel Dynamic Acceleration Technology mode, it is possible for both cores to be active under certain internal conditions. In such a scenario the processor may draw a Instantaneous current (ICC_CORE_INST) for a short duration of tINST; however, the average ICC current will be lesser than or equal to ICCDES current specification. Please refer to the Processor DC Specifications section for more details. 2.
Low Power Features 24 Datasheet
Electrical Specifications 3 Electrical Specifications 3.1 Power and Ground Pins For clean, on-chip power distribution, the processor will have a large number of VCC (power) and VSS (ground) inputs. All power pins must be connected to VCC power planes while all VSS pins must be connected to system ground planes. Use of multiple power and ground planes is recommended to reduce I*R drop. The processor VCC pins must be supplied the voltage determined by the VID (Voltage ID) pins. 3.
Electrical Specifications 3.3 Voltage Identification and Power Sequencing The processor uses seven voltage identification pins,VID[6:0], to support automatic selection of power supply voltages. The VID pins for the processor are CMOS outputs driven by the processor VID circuitry. Table 2 specifies the voltage level corresponding to the state of VID[6:0]. A 1 in the table refers to a high-voltage level and a 0 refers to a low-voltage level. Table 2.
Electrical Specifications Table 2. Voltage Identification Definition (Sheet 2 of 3) VID6 VID5 VID4 VID3 VID2 VID1 VID0 VCC (V) 0 1 0 1 0 0 0 1.0000 0 1 0 1 0 0 1 0.9875 0 1 0 1 0 1 0 0.9750 0 1 0 1 0 1 1 0.9625 0 1 0 1 1 0 0 0.9500 0 1 0 1 1 0 1 0.9375 0 1 0 1 1 1 0 0.9250 0 1 0 1 1 1 1 0.9125 0 1 1 0 0 0 0 0.9000 0 1 1 0 0 0 1 0.8875 0 1 1 0 0 1 0 0.8750 0 1 1 0 0 1 1 0.8625 0 1 1 0 1 0 0 0.
Electrical Specifications Table 2. 28 Voltage Identification Definition (Sheet 3 of 3) VID6 VID5 VID4 VID3 VID2 VID1 VID0 VCC (V) 1 0 1 0 1 1 1 0.4125 1 0 1 1 0 0 0 0.4000 1 0 1 1 0 0 1 0.3875 1 0 1 1 0 1 0 0.3750 1 0 1 1 0 1 1 0.3625 1 0 1 1 1 0 0 0.3500 1 0 1 1 1 0 1 0.3375 1 0 1 1 1 1 0 0.3250 1 0 1 1 1 1 1 0.3125 1 1 0 0 0 0 0 0.3000 1 1 0 0 0 0 1 0.2875 1 1 0 0 0 1 0 0.2750 1 1 0 0 0 1 1 0.
Electrical Specifications 3.4 Catastrophic Thermal Protection The processor supports the THERMTRIP# signal for catastrophic thermal protection. An external thermal sensor should also be used to protect the processor and the system against excessive temperatures. Even with the activation of THERMTRIP#, which halts all processor internal clocks and activity, leakage current can be high enough that the processor cannot be protected in all conditions without the removal of power to the processor.
Electrical Specifications 3.7 FSB Signal Groups The FSB signals have been combined into groups by buffer type in the following sections. In this document, the term “AGTL+ Input” refers to the AGTL+ input group as well as the AGTL+ I/O group when receiving. Similarly, “AGTL+ Output” refers to the AGTL+ output group as well as the AGTL+ I/O group when driving. With the implementation of a source-synchronous data bus, two sets of timing parameters are specified.
Electrical Specifications 1. 2. Refer to Chapter 4 for signal descriptions and termination requirements. In processor systems where there is no debug port implemented on the system board, these signals are used to support a debug port interposer. In systems with the debug port implemented on the system board, these signals are no connects. BPM[2:1]# and PRDY# are AGTL+ output-only signals. PROCHOT# signal type is open drain output and CMOS input. On-die termination differs from other AGTL+ signals. 3. 4.
Electrical Specifications 2. 3. 4. 5. 6. 3.10 Excessive overshoot or undershoot on any signal will likely result in permanent damage to the processor. Storage temperature is applicable to storage conditions only. In this scenario, the processor must not receive a clock, and no lands can be connected to a voltage bias. Storage within these limits will not affect the long-term reliability of the device. For functional operation, please refer to the processor case temperature specifications.
Electrical Specifications Table 6. Voltage and Current Specifications for the Dual-Core, Extreme Edition Processors (Sheet 2 of 2) Symbol Parameter Min Typ Max Unit Notes IAH, ISGNT ICC Auto-Halt & Stop-Grant HFM SuperLFM — — 29.7 16.7 A 3, 4, 10 ISLP ICC Sleep HFM SuperLFM — — 28.8 16.5 A 3, 4, 10 IDSLP ICC Deep Sleep HFM SuperLFM — — 26.8 16.0 A 3, 4, 10 IDPRSLP ICC Deeper Sleep (C4) — — 12.2 A 3, 4 IDC4 ICC Intel Enhanced Deeper Sleep State — — 11.
Electrical Specifications Table 7. Voltage and Current Specifications for the Dual-Core, Standard-Voltage Processors Symbol Parameter Min Typ Max Unit Notes VCCDAM VCC in Enhanced Intel® Dynamic Acceleration Technology Mode 1.0 1.3 V 1, 2 VCCHFM VCC at Highest Frequency Mode (HFM) 1.0 1.25 V 1, 2 VCCLFM VCC at Lowest Frequency Mode (LFM) 0.85 — 1.1 V 1, 2 0.75 — 0.95 V 1, 2 — 1.2 — V 2, 6 1.0 1.05 1.1 V 1.425 1.5 1.575 V 0.65 — 0.85 V 1, 2 0.6 — 0.
Electrical Specifications 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. Each processor is programmed with a maximum valid voltage identification value (VID), which is set at manufacturing and cannot be altered. Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the VID range.
Electrical Specifications Table 8. Voltage and Current Specifications for the Dual-Core, Low-Power Standard-Voltage Processors (25 W) in Standard Package Symbol Parameter Min Typ Max Unit Notes IAH, ISGNT ICC Auto-Halt & Stop-Grant HFM SuperLFM — — 15.3 10.5 A 3, 4, 10 ISLP ICC Sleep HFM SuperLFM — — 14.6 10.3 A 3, 4, 10 IDSLP ICC Deep Sleep HFM SuperLFM — — 12.9 9.8 A 3, 4, 10 IDPRSLP ICC Deeper Sleep — — 7.3 A 3, 4 IDC4 ICC Intel Enhanced Deeper Sleep — — 6.
Electrical Specifications Table 9. Voltage and Current Specifications for the Dual-Core, Power Optimized Performance (25 W) SFF Processors Symbol Parameter Min Typ Max Unit Notes VCCDAM VCC in Enhanced Intel® Dynamic Acceleration Technology Mode 0.9 — 1.275 V 1, 2 VCCHFM VCC at Highest Frequency Mode (HFM) 0.9 — 1.2125 V 1, 2 VCCLFM VCC at Lowest Frequency Mode (LFM) 0.85 — 1.025 V 1, 2 VCCSLFM VCC at Super Low Frequency Mode (Super LFM) 0.75 — 0.
Electrical Specifications 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. that this differs from the VID employed by the processor during a power management event (Intel Thermal Monitor 2, Enhanced Intel SpeedStep Technology, or Enhanced Halt State). The voltage specifications are assumed to be measured across VCC_SENSE and VSS_SENSE pins at socket with a 100-MHz bandwidth oscilloscope, 1.5-pF maximum probe capacitance, and 1-MΩ minimum impedance.
Electrical Specifications Table 10. Voltage and Current Specifications for the Dual-Core, Low-Voltage SFF Processor Symbol Parameter Min Typ Max Unit Notes IDSLP ICC Deep Sleep HFM SuperLFM — — 10.5 7.5 A 3, 4, 12 IDPRSLP ICC Deeper Sleep — — 6.5 A 3, 4 IDC4 ICC Intel Enhanced Deeper Sleep — — 5.6 A 3, 4 IDPWDN ICC Deep Power Down Technology State (C6) — — 3.
Electrical Specifications Table 11. Voltage and Current Specifications for the Dual-Core, Ultra-Low-Voltage SFF Processor Symbol Parameter VCCDAM VCC in Enhanced Intel® Dynamic Acceleration Technology Mode Min Typ Max Unit Notes 0.8 — 1.1625 V 1, 2 VCCHFM VCC at Highest Frequency Mode (HFM) 0.775 — 1.1 V 1, 2 VCCLFM VCC at Lowest Frequency Mode (LFM) 0.8 — 0.975 V 1, 2 VCCSLFM VCC at Super Low Frequency Mode (Super LFM) 0.725 — 0.
Electrical Specifications 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. Each processor is programmed with a maximum valid voltage identification value (VID), which is set at manufacturing and cannot be altered. Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the VID range.
Electrical Specifications Table 12. Voltage and Current Specifications for the Ultra-Low-Voltage, Single-Core (5.5 W) SFF Processor Symbol Parameter Min Typ Max Unit Notes IDSLP ICC Deep Sleep HFM SuperLFM — — 3.3 3.0 A 3, 4, 12 IDPRSLP ICC Deeper Sleep — — 2.1 A 3, 4 IDC4 ICC Intel Enhanced Deeper Sleep State — — 1.9 A 3, 4 IDPWDN ICC Deep Power Down Technology State (C6) — — 1.
Electrical Specifications Figure 4. Active VCC and ICC Loadline for Standard Voltage, Low-Power SV (25 W) and Dual-Core, Extreme Edition Processors VCC-CORE [V] Slope = -2.1 mV/A at package VccSense, VssSense pins. Differential Remote Sense required. VCC-CORE max {HFM|LFM} VCC-CORE, DC max {HFM|LFM} 10mV= RIPPLE VCC-CORE nom {HFM|LFM} VCC-CORE, DC min {HFM|LFM} VCC-CORE min {HFM|LFM} +/-VCC-CORE Tolerance = VR St. Pt.
Electrical Specifications Figure 5. Deeper Sleep VCC and ICC Loadline for Standard-Voltage, Low-Power SV (25 W) and Dual-Core Extreme Edition Processors VCC-CORE [V] Slope = -2.1 mV/A at package VccSense, VssSense pins. Differential Remote Sense required. VCC-CORE max {HFM|LFM} VCC-CORE, DC max {HFM|LFM} 13mV= RIPPLE VCC-CORE nom {HFM|LFM} VCC-CORE, DC min {HFM|LFM} VCC-CORE min {HFM|LFM} +/-VCC-CORE Tolerance = VR St. Pt.
Electrical Specifications Figure 6. Deeper Sleep VCC and ICC Loadline for Low-Power Standard-Voltage Processors VCC-CORE [V] Slope = -4.0 mV/A at package VccSense, VssSense pins. Differential Remote Sense required. VCC-CORE max {HFM|LFM} VCC-CORE, DC max {HFM|LFM} 10mV= RIPPLE VCC-CORE nom {HFM|LFM} VCC-CORE, DC min {HFM|LFM} +/-VCC-CORE Tolerance = VR St. Pt.
Electrical Specifications Figure 7. Active VCC and ICC Loadline for Low-Voltage, Ultra-Low-Voltage and Power Optimized Performance Processor VCC-CORE [V] Slope = -4.0 mV/A at package VccSense, VssSense pins. Differential Remote Sense required. VCC-CORE max {HFM|LFM} VCC-CORE, DC max {HFM|LFM} 10mV= RIPPLE VCC-CORE nom {HFM|LFM} VCC-CORE, DC min {HFM|LFM} VCC-CORE min {HFM|LFM} +/-VCC-CORE Tolerance = VR St. Pt.
Electrical Specifications Figure 8. Deeper Sleep VCC and ICC Loadline for Low-Voltage, Ultra-Low-Voltage and Power Optimized Performance Processor VCC-CORE [V] Slope = -4.0 mV/A at package VccSense, VssSense pins. Differential Remote Sense required. VCC-CORE max {HFM|LFM} VCC-CORE, DC max {HFM|LFM} 10mV= RIPPLE VCC-CORE nom {HFM|LFM} VCC-CORE, DC min {HFM|LFM} +/-VCC-CORE Tolerance = VR St. Pt.
Electrical Specifications Table 13. Symbol VCCP GTLREF AGTL+ Signal Group DC Specifications Parameter I/O Voltage Reference Voltage Min Typ Max Unit 1.00 1.05 1.10 V Notes1 0.65 0.70 0.72 V 6 27.23 27.5 27.78 Ω 10 Termination Resistor Address 49 55 63 Ω 11, 12 Termination Resistor Data 49 55 63 Ω 11, 13 RCOMP Compensation Resistor RODT/A RODT/D 49 55 63 Ω 11, 14 VIH Input High Voltage 0.82 1.05 1.20 V 3,6 VIL Input Low Voltage -0.10 0 0.
Electrical Specifications Table 14. CMOS Signal Group DC Specifications Symbol VCCP Parameter I/O Voltage Min Typ Max Unit 1.00 1.05 1.10 V Notes1 VIL Input Low Voltage CMOS -0.10 0.00 0.3*VCCP V 2 VIH Input High Voltage 0.7*VCCP VCCP VCCP+0.1 V 2 VOL Output Low Voltage -0.10 0 0.1*VCCP V 2 VOH Output High Voltage 0.9*VCCP VCCP VCCP+0.1 V 2 IOL Output Low Current 1.5 — 4.1 mA 3 IOH Output High Current 1.5 — 4.
Electrical Specifications 50 Datasheet
Package Mechanical Specifications and Pin Information 4 Package Mechanical Specifications and Pin Information 4.1 Package Mechanical Specifications The processor (XE and SV) is available in 478-pin Micro-FCPGA packages as well as 479-ball Micro-FCBGA packages. The package mechanical dimensions are shown in Figure 9 through Figure 13. The processor (POP, LV, ULV DC and ULV SC) is available 956-ball Micro-FCBGA packages. The package mechanical dimensions are shown in Figure 14 and Figure 15.
C2 B A C1 52 FRONT VIEW A B2 Package Substrate 0.65 MAX 0.37 MAX Underfill A DETAIL SCALE 20 Die SIDE VIEW 478 PINS P F2 J1 F3 2.03±0.08 0.65 MAX J2 C H1 1.27 BASIC 1.27 BASIC J1 J2 W Keying Pins 0.355 15.875 BASIC H2 6g 15.875 BASIC H1 0.255 31.75 BASIC P 31.75 BASIC G2 2.102 0.88 G1 1.862 12.4 F2 F3 C2 35.05 8.7 34.95 MAX 35.05 C1 B2 MIN MILLIMETERS 34.95 B1 SYMBOL BOTTOM VIEW G1 H2 G2 B6887-01 D76563(1) M C A B M C A1, A2 ø0.356 ø0.
C2 B Datasheet A FRONT VIEW TOP VIEW ø0.65 MAX ø0.37 MAX Package Substrate A B2 A DETAIL SCALE 20 Underfill Die SIDE VIEW øP 478 PINS F2 J2 F3 2.03±0.08 0.65 MAX J1 C H1 MIN F3 35.05 1.962 W P 6g Keying Pins 0.255 0.355 1.27 BASIC 1.27 BASIC J1 J2 15.875 BASIC H2 31.75 BASIC 15.875 BASIC H1 31.75 BASIC G2 G1 1.742 9.4 MAX 35.05 0.88 C2 34.95 34.95 8.7 F2 H2 MILLIMETERS C1 B2 B1 SYMBOL BOTTOM VIEW G1 G2 M C A B M C A1, A2 ø0.356 ø0.
EDGE KEEP OUT ZONE 4X 54 4X 5.00 4X 7.00 SIDE VIEW 1.5 MAX ALLOWABLE COMPONENT HEIGHT ø0.305±0.25 ø0.406 M C A B ø0.254 M C BOTTOM VIEW 6.985 13.97 1.625 6.985 13.97 1.625 B6740-01 D76564(2) Figure 11. TOP VIEW CORNER KEEP OUT ZONE 4X 4X 7.
C2 Datasheet A DETAIL B SCALE 50 øM FRONT VIEW TOP VIEW C1 B1 A B2 W 6g 1.27 BASIC J2 0.8 0.69 1.27 BASIC J1 0.6 15.875 BASIC H2 N 15.875 BASIC H1 0.61 31.75 BASIC M 31.75 BASIC G2 2.207 G1 1.937 0.88 F2 F3 8.7 9.4 35.05 C1 34.95 B2 MAX 35.05 C2 34.95 MIN MILLIMETERS B1 SYMBOL SIDE VIEW ø0.203 ø0.071 B L C A B L COMMENTS 479 BALLS SEE DETAIL J2 N Package Substrate J1 H1 Die DETAIL A SCALE 20 Underfill BOTTOM VIEW G1 F2 H2 C 0.
EDGE KEEP OUT ZONE 4X 56 4X 5.00 4X 7.00 SIDE VIEW 0.55 MAX ALLOWABLE COMPONENT HEIGHT 13.97 BOTTOM VIEW 6.985 1.625 6.985 13.97 1.625 B6742-01 D93702(2) Figure 13. TOP VIEW CORNER KEEP OUT ZONE 4X 4X 7.
Datasheet #$%& '() "*+,, FRONT VIEW : TOP VIEW !" ! - . . / A + DETAIL / SIDE VIEW B 3 ; 4 : 0 3 ; 4 : 0 DETAIL - . 1/ 8 ' 6 1 8 ' 6 1 ø0.39±0.02 (Solder Resist Opening) (Metal Diameter) BOTTOM VIEW ø0.46±0.04 1 1/ 2 . 2 . 2/ . 0 0/ 1 . / 2 . 2/ .
: FRONT VIEW TOP VIEW ! "#$%& %! '()* +,-!&./00 A /! DETAIL SIDE VIEW B DETAIL 2 3 ; 4 : 1 3 ; 4 : 1 8 + 6 2 8 + 6 2 (Solder Resist Opening) ø0.39±0.02 (Metal Diameter) BOTTOM VIEW ø0.46±0.
Package Mechanical Specifications and Pin Information 4.2 Processor Pinout and Pin List Figure 16 and Figure 17 show the processor (SV and XE) pinout as viewed from the top of the package. Table 16 provides the pin list, arranged numerically by pin number. Figure 16 through Figure 18 show the top view of the LV and ULV processor package. Table 18 lists the SFF processor ballout alphabetically by signal name. For signal descriptions, refer to Section 4.3. Figure 16.
Package Mechanical Specifications and Pin Information Figure 17.
Package Mechanical Specifications and Pin Information Table 16. Table 16.
Package Mechanical Specifications and Pin Information Table 16. 62 Pin Name Listing Pin Name Pin # Signal Buffer Type BPRI# G5 Common Clock BR0# F1 BSEL[0] Table 16.
Package Mechanical Specifications and Pin Information Table 16. Pin Name Pin # Signal Buffer Type Direction D[36]# V23 Source Synch D[37]# T22 D[38]# Table 16.
Package Mechanical Specifications and Pin Information Table 16. Pin Name Pin # Signal Buffer Type Direction DSTBP[2]# AA26 Source Synch DSTBP[3]# AF24 FERR# Table 16.
Package Mechanical Specifications and Pin Information Table 16. Datasheet Pin Name Listing Pin Name Pin # Signal Buffer Type VCC A9 VCC Table 16.
Package Mechanical Specifications and Pin Information Table 16. 66 Pin Name Listing Pin Name Pin # Signal Buffer Type VCC AE12 VCC Table 16.
Package Mechanical Specifications and Pin Information Table 16. Datasheet Pin Name Listing Pin Name Pin # Signal Buffer Type VCC E18 VCC Table 16.
Package Mechanical Specifications and Pin Information Table 16. 68 Pin Name Listing Pin Name Pin # Signal Buffer Type VSS AA2 VSS Table 16.
Package Mechanical Specifications and Pin Information Table 16. Datasheet Pin Name Listing Pin Name Pin # Signal Buffer Type VSS AE26 VSS Table 16.
Package Mechanical Specifications and Pin Information Table 16. 70 Pin Name Listing Pin Name Pin # Signal Buffer Type VSS E24 VSS Table 16.
Package Mechanical Specifications and Pin Information Table 16. Datasheet Pin Name Listing Pin Name Pin # Signal Buffer Type VSS R22 VSS Table 16.
Package Mechanical Specifications and Pin Information Table 17. 72 Table 17.
Package Mechanical Specifications and Pin Information Table 17. Table 17.
Package Mechanical Specifications and Pin Information Table 17. Pin # Pin Name Signal Buffer Type AE13 VCC Power/Other AE14 VSS Power/Other AE15 VCC Power/Other Table 17.
Package Mechanical Specifications and Pin Information Table 17. Datasheet Pin # Listing Pin # Pin Name Signal Buffer Type C8 VSS Power/Other Table 17.
Package Mechanical Specifications and Pin Information Table 17. Pin # Pin Name Signal Buffer Type Table 17.
Package Mechanical Specifications and Pin Information Table 17. Table 17.
Package Mechanical Specifications and Pin Information Table 17. Table 17.
Package Mechanical Specifications and Pin Information Table 17.
Package Mechanical Specifications and Pin Information Figure 18.
Package Mechanical Specifications and Pin Information Figure 19.
Package Mechanical Specifications and Pin Information Figure 20.
Package Mechanical Specifications and Pin Information Figure 21.
Package Mechanical Specifications and Pin Information Table 18.
Package Mechanical Specifications and Pin Information Table 18.
Package Mechanical Specifications and Pin Information Table 18.
Package Mechanical Specifications and Pin Information Table 18.
Package Mechanical Specifications and Pin Information Table 18.
Package Mechanical Specifications and Pin Information Table 18.
Package Mechanical Specifications and Pin Information Table 18.
Package Mechanical Specifications and Pin Information Table 18.
Package Mechanical Specifications and Pin Information Table 18.
Package Mechanical Specifications and Pin Information 4.3 Alphabetical Signals Reference Table 19. Signal Description (Sheet 1 of 8) Name A[35:3]# A20M# Type Description Input/ Output A[35:3]# (Address) define a 236-byte physical memory address space. In sub-phase 1 of the address phase, these pins transmit the address of a transaction. In sub-phase 2, these pins transmit transaction type information. These signals must connect the appropriate pins of both agents on the processor FSB.
Package Mechanical Specifications and Pin Information Table 19. Signal Description (Sheet 2 of 8) Name Type Description BPRI# Input BPRI# (Bus Priority Request) is used to arbitrate for ownership of the FSB. It must connect the appropriate pins of both FSB agents. Observing BPRI# active (as asserted by the priority agent) causes the other agent to stop issuing new requests, unless such requests are part of an ongoing locked operation.
Package Mechanical Specifications and Pin Information Table 19. Signal Description (Sheet 3 of 8) Name DEFER# Type Description Input DEFER# is asserted by an agent to indicate that a transaction cannot be ensured in-order completion. Assertion of DEFER# is normally the responsibility of the addressed memory or input/ output agent. This signal must connect the appropriate pins of both FSB agents. DINV[3:0]# (Data Bus Inversion) are source synchronous and indicate the polarity of the D[63:0]# signals.
Package Mechanical Specifications and Pin Information Table 19. Signal Description (Sheet 4 of 8) Name Type Description Data strobe used to latch in D[63:0]#. Signals DSTBP[3:0]# FERR#/PBE# Input/ Output Output Associated Strobe D[15:0]#, DINV[0]# DSTBP[0]# D[31:16]#, DINV[1]# DSTBP[1]# D[47:32]#, DINV[2]# DSTBP[2]# D[63:48]#, DINV[3]# DSTBP[3]# FERR# (Floating-point Error)/PBE# (Pending Break Event) is a multiplexed signal and its meaning is qualified with STPCLK#.
Package Mechanical Specifications and Pin Information Table 19. Signal Description (Sheet 5 of 8) Name INIT# Type Input Description INIT# (Initialization), when asserted, resets integer registers inside the processor without affecting its internal caches or floating-point registers. The processor then begins execution at the power-on Reset vector configured during power-on configuration. The processor continues to handle snoop requests during INIT# assertion. INIT# is an asynchronous signal.
Package Mechanical Specifications and Pin Information Table 19. Signal Description (Sheet 6 of 8) Name PWRGOOD Type Input Description PWRGOOD (Power Good) is a processor input. The processor requires this signal to be a clean indication that the clocks and power supplies are stable and within their specifications. ‘Clean’ implies that the signal remains low (capable of sinking leakage current), without glitches, from the time that the power supplies are turned on until they come within specification.
Package Mechanical Specifications and Pin Information Table 19. Signal Description (Sheet 7 of 8) Name Type Description STPCLK# Input STPCLK# (Stop Clock), when asserted, causes the processor to enter a low power Stop-Grant state. The processor issues a StopGrant Acknowledge transaction, and stops providing internal clock signals to all processor core units except the FSB and APIC units. The processor continues to snoop bus transactions and service interrupts while in Stop-Grant state.
Package Mechanical Specifications and Pin Information Table 19. Signal Description (Sheet 8 of 8) Name Type Description Output VCCSENSE together with VSSSENSE are voltage feedback signals that control the 2.1 mΩ loadline at the processor die. It should be used to sense voltage near the silicon with little noise. VID[6:0] Output VID[6:0] (Voltage ID) pins are used to support automatic selection of power supply voltages (VCC).
Thermal Specifications and Design Considerations 5 Thermal Specifications and Design Considerations A complete thermal solution includes both component and system-level thermal management features.
Thermal Specifications and Design Considerations Table 21. Power Specifications for the Dual-Core Standard Voltage Processor Symbol TDP Processor Number T9900 T9800 T9600 T9550 T9400 Core Frequency & Voltage 3.06 GHz & VCCHFM 2.93 GHz & VCCHFM 2.80 GHz & VCCHFM 2.66 GHz & VCCHFM 2.53 GHz & VCCHFM 1.6 GHz & VCCLFM 35 0.8 GHz & VCCSLFM 12 Symbol PAH, PSGNT Thermal Design Power Parameter Unit Notes W 1, 4, 5, 6 35 35 35 35 22 Min Typ Max Unit Notes — — 13.
Thermal Specifications and Design Considerations Table 22. Power Specifications for the Dual-Core Low Power Standard Voltage Processors (25W) in Standard Package Symbol TDP Processor Number P9700 P9600 P8800 P9500 P8700 P8600 P8400 Core Frequency & Voltage PSGNT Parameter Unit Notes W 1, 4, 5, 6 25 2.8 GHz & VCCHFM 2.667 GHz & VCCHFM 2.667 GHz & VCCHFM 2.53 GHz & VCCHFM 2.53 GHz & VCCHFM 2.4 GHz & VCCHFM 2.267 GHz & VCCHFM 1.6 GHz & VCCLFM 0.
Thermal Specifications and Design Considerations Table 23. Symbol TDP Power Specifications for the Dual-Core Power Optimized Performance (25 W) SFF Processors Processor Number PSGNT Thermal Design Power SP9600 2.53 GHz & HFM VCC 25 SP9400 2.4 GHz & HFM VCC 2.26 GHz & HFM VCC 25 1.6 GHz & Super LFM VCC 0.8 GHz & Super LFM VCC 20 SP9300 Symbol PAH, Core Frequency & Voltage Parameter Unit Notes W 1, 4, 5, 6 Max Unit Notes 8.
Thermal Specifications and Design Considerations Table 24. Symbol Power Specifications fro the Dual-Core Low Voltage (LV) SFF Processors Processor Number SL9600 SL9400 TDP SL9300 Core Frequency & Voltage Thermal Design Power Unit Notes W 1, 4, 5, 6 17 2.13 GHz & HFM VCC 1.86 GHz & HFM VCC 1.6 GHz & HFM VCC 1.6 GHz & Super LFM VCC 0.8 GHz & Super LFM VCC 17 17 16.7 10 Symbol PAH, PSGNT Parameter Min Typ Max Unit Notes — — 6.
Thermal Specifications and Design Considerations Table 25. Symbol TDP Power Specifications for the Dual-Core Ultra-Low-Voltage (ULV) Processors Processor Number SU9600 SU9400 SU9300 Symbol PAH, PSGNT Core Frequency & Voltage Thermal Design Power 1.4 GHz & HFM VCC 10 1.4 GHz & HFM VCC 10 1.2GHz & HFM VCC 10 1.2 GHz & Super LFM VCC 10 0.8 GHz & Super LFM VCC 8 Parameter Notes W 1, 4, 5, 6 Min Typ Max Unit Notes — — 2.
Thermal Specifications and Design Considerations Table 26. Symbol TDP Power Specifications for the Single-Core Ultra-Low-Voltage (5.5 W) SFF Processors Processor Number PSGNT Thermal Design Power SU3500 1.4 GHz & HFM VCC 5.5 SU3300 1.2 GHz & HFM VCC 1.2 GHz & Super LFM VCC 0.8 GHz & Super LFM VCC 5.5 Symbol PAH, Core Frequency & Voltage Parameter 5.5 Unit Notes W 1, 4, 5, 6 5 Min Typ Max Unit Notes — — 2.
Thermal Specifications and Design Considerations 5.1 Monitoring Die Temperature The processor incorporates three methods of monitoring die temperature: • Thermal Diode • Intel® Thermal Monitor • Digital Thermal Sensor 5.1.1 Thermal Diode Intel’s processors utilize an SMBus thermal sensor to read back the voltage/current characteristics of a substrate PNP transistor. Since these characteristics are a function of temperature, these parameters can be used to calculate silicon temperature values.
Thermal Specifications and Design Considerations Table 28. Thermal Diode Parameters Using Transistor Model Symbol Parameter IFW Forward Bias Current IE Emitter Current nQ Transistor Ideality Beta RT Series Resistance Min Typ Max Unit 5 — 200 μA 1 μA 1 5 — 200 0.997 1.001 1.008 0.1 0.4 0.5 3.0 4.5 7.0 Notes 2, 3, 4 2, 3 Ω 2 NOTES: 1. Intel does not support or recommend operation of the thermal diode under reverse bias. 2.
Thermal Specifications and Design Considerations active/inactive transitions of the TCC when the processor temperature is near the trip point. The duty cycle is factory configured and cannot be modified. Also, automatic mode does not require any additional hardware, software drivers, or interrupt handling routines. Processor performance will be decreased by the same amount as the duty cycle when the TCC is active.
Thermal Specifications and Design Considerations Besides the thermal sensor and thermal control circuit, the Intel Thermal Monitor also includes one ACPI register, one performance counter register, three MSR, and one I/O pin (PROCHOT#). All are available to monitor and control the state of the Intel Thermal Monitor feature. The Intel Thermal Monitor can be configured to generate an interrupt upon the assertion or deassertion of PROCHOT#.
Thermal Specifications and Design Considerations Changes to the temperature can be detected via two programmable thresholds located in the processor MSRs. These thresholds have the capability of generating interrupts via the core's local APIC. Refer to the Intel® 64 and IA-32 Architectures Software Developer's Manuals for specific register and programming details. 5.2 Out of Specification Detection Overheat detection is performed by monitoring the processor temperature and temperature gradient.
Thermal Specifications and Design Considerations of time when running the most power-intensive applications. An under-designed thermal solution that is not able to prevent excessive assertion of PROCHOT# in the anticipated ambient environment may cause a noticeable performance loss.
