Datasheet

Errata
92 Specification Update
AH4P Multi-Core Processors Configured for Single Core Operation May Not
Be Able to Enter Intel
®
Enhanced Deeper Sleep
Problem: BIOS may contain the option to disable CMP (Core Multiple Processing). Disabling CMP
configures a processor for single core operation. Due to this erratum, a multi-core
processor operating with CMP disabled may not be able to enter Intel
®
Enhanced
Deeper Sleep if a SIPI (Start-up Inter-Processor Interrupt) is sent to the disabled
processor.
Implication: When this erratum occurs, the processor may not be able to enter the Intel
®
Enhanced Deeper Sleep and therefore may consume more power than expected. Intel
has not observed this erratum with any commercially available system or software.
Workaround: None Identified
Status: For the affected steppings, see the Summary Tables of Changes
AH5P VTPR Access May Lead to System Hang
Problem: The logical processor may hang if an instruction performs a VTPR access and the next
instruction to be executed is located on a different code page.
Implication: Software running VMX non-root operation may cause a logical processor to hang if the
virtual-machine monitor (VMM) sets both the “use TPR shadow” and “virtualize APIC
accesses” VM-execution controls.
Workaround: It is possible for the BIOS to contain a workaround for this erratum
Status: For the affected steppings, see the Summary Tables of Changes