Datasheet

Errata
Specification Update 87
AH115 VM Exit with Exit Reason “TPR Below Threshold” Can Cause the
Blocking by MOV/POP SS and Blocking by STI Bits to Be Cleared in the
Guest Interruptibility-State Field
Problem: As specified in Section, “VM Exits Induced by the TPR Shadow”, in the Intel
®
64 and
IA-32 Architectures Software Developer’s Manual, Volume 3B, a VM exit occurs
immediately after any VM entry performed with the “use TPR shadow", "activate
secondary controls”, and “virtualize APIC accesses” VM-execution controls all set to 1
and with the value of the TPR shadow (bits 7:4 in byte 80H of the virtual-APIC page)
less than the TPR-threshold VM-execution control field. Due to this erratum, such a VM
exit will clear bit 0 (blocking by STI) and bit 1 (blocking by MOV/POP SS) of the
interruptibility-state field of the guest-state area of the VMCS (bit 0 - blocking by STI
and bit 1 - blocking by MOV/POP SS should be left unmodified).
Implication: Since the STI, MOV SS, and POP SS instructions cannot modify the TPR shadow, bits
1:0 of the interruptibility-state field will usually be zero before any VM entry meeting
the preconditions of this erratum; behavior is correct in this case. However, if VMM
software raises the value of the TPR-threshold VM-execution control field above that of
the TPR shadow while either of those bits is 1, incorrect behavior may result. This may
lead to VMM software prematurely injecting an interrupt into a guest. Intel has not
observed this erratum with any commercially available software.
Workaround: VMM software raising the value of the TPR-threshold VM-execution control field should
compare it to the TPR shadow. If the threshold value is higher, software should not
perform a VM entry; instead, it could perform the actions that it would normally take
in response to a VM exit with exit reason “TPR below threshold”.
Status: For the steppings affected, see the Summary Tables of Changes.
AH116 Using Memory Type Aliasing with Cacheable and WC Memory Types
May Lead to Memory Ordering Violations
Problem: Memory type aliasing occurs when a single physical page is mapped to two or more
different linear addresses, each with different memory types. Memory type aliasing
with a cacheable memory type and WC (write combining) may cause the processor to
perform incorrect operations leading to memory ordering violations for WC
operations.
Implication: Software that uses aliasing between cacheable and WC memory types may observe
memory ordering errors within WC memory operations. Intel has not observed this
erratum with any commercially available software.
Workaround: None identified. Intel does not support the use of cacheable and WC memory type
aliasing, and WC operations are defined as weakly ordered.
Status: For the steppings affected, see the Summary Tables of Changes.