Datasheet

Errata
84 Specification Update
AH108. Overlap of an Intel
®
VT APIC Access Page in a Guest with the DS Save
Area May Lead to Unpredictable Behavior
Problem: Logging of a branch record or a PEBS (precise-event-based-sampling) record to the
DS (debug store) save area that overlaps with the APIC access page may lead to
unpredictable behavior.
Implication: Guest software configured to log branch records or PEBS records cannot specify the
DS (debug store) save area within the APIC-access page. Under any expected usage
model this type of overlap is not expected to exist. One should be aware of the fact
that the specified DS address is of linear form while the APIC access page is of a
physical form. Any solution that wishes to avoid this condition will need to
comprehend the linear-to-physical translation of the DS related address pointers with
respect to the mapping of the physical APIC access page to avoid such an overlap.
Under normal circumstances for correctly written software, such an overlap is not
expected to exist. Intel has not observed this erratum with any commercially available
software.
Workaround: For a fully comprehensive workaround, the VMM should not allow the logging of
branch or PEBS records while guest software is running if the "virtualize APIC
accesses" VM-execution control is 1.
Status: For the steppings affected, see the Summary Tables of Changes.
AH109. VTPR Write Access during Event Delivery May Cause an APIC-Access
VM Exit
Problem: VTPR write accesses should not cause APIC-access VM exits but instead should cause
data to be written to the virtual-APIC page. Due to this erratum, a VTPR write access
during event delivery may cause an APIC-access VM exit with no data being written to
the virtual-APIC page.
Implication: VTPR accesses are accesses to offset 80H on the APIC-access page. VTPR write
accesses can occur during event delivery when pushing data on the stack. Because
event delivery performs multiple stack pushes, an event delivery that includes a VTPR
write access will also include at least one other write to the APIC-access page. That
other write will cause an APIC-access VM exit. Thus, even in the presence of this
erratum, any event delivery that includes a VTPR write access will cause an APIC-
access VM exit. The only difference with respect to correct behavior will be with regard
to page offset saved in the exit qualification by the APIC-access VM exit. A VMM
should be able to emulate the event delivery correctly even with the incorrect offset.
Workaround: The VMM should emulate any event delivery that causes an APIC-access VM exit in the
same way regardless of the offset saved in the exit qualification.
Status: For the steppings affected, see the Summary Tables of Changes.