Datasheet

Errata
80 Specification Update
AH99. Performance Monitoring Event CPU_CLK_UNHALTED.REF May Not
Count Clock Cycles According to the Processors Operating Frequency
Problem: Performance Counter MSR_PERF_FIXED_CTR2 (MSR 30BH) that counts
CPU_CLK_UNHALTED.REF clocks should count these clock cycles at a constant rate
that is determined by the maximum resolved boot frequency, as programmed by
BIOS. Due to this erratum, the rate is instead set by the maximum core-clock to bus-
clock ratio of the processor, as indicated by hardware.
Implication: No functional impact as a result of this erratum. If the maximum resolved boot
frequency as programmed by BIOS is different from the frequency implied by the
maximum core-clock to bus-clock ratio of the processor as indicated by hardware,
then the following effects may be observed:
Workaround: Performance Monitoring Event CPU_CLK_UNHALTED.REF will count at a rate different
than the TSC (Time Stamp Counter)
When running a system with several processors that have different maximum
core-clock to bus-clock ratios, CPU_CLK_UNHALTED.REF monitoring events at
each processor will be counted at different rates and therefore will not be
comparable.
Calculate the ratio of the rates at which the TSC and the CPU_CLK_UNHALTED.REF
performance monitoring event count (this can be done by measuring
simultaneously their counted value while executing code) and adjust the
CPU_CLK_UNHALTED.REF event count to the maximum resolved boot frequency
using this ratio.
Status: For the steppings affected, see the Summary Tables of Changes.
AH100. Store Ordering May Be Incorrect between WC and WP Memory Types
Problem: According to Intel
®
64 and IA-32 Architectures Software Developer's Manual, Volume
3A, Methods of Caching Available, WP (Write Protected) stores should drain the WC
(Write Combining) buffers in the same way as UC (Uncacheable) memory type stores
do. Due to this erratum, WP stores may not drain the WC buffers.
Implication: Memory ordering may be violated between WC and WP stores.
Workaround: None Identified
Status: For the steppings affected, see the Summary Tables of Changes.