Datasheet

Errata
74 Specification Update
AH84. Non-Temporal Data Store May Be Observed in Wrong Program Order
Problem: When non-temporal data is accessed by multiple read operations in one thread while
another thread performs a cacheable write operation to the same address, the data
stored may be observed in wrong program order (i.e., later load operations may read
older data).
Implication: Software that uses non-temporal data without proper serialization before accessing
the non-temporal data may observe data in wrong program order.
Workaround: Software that conforms to the Intel
®
64 and IA-32 Architecture Software Developer's
Manual, Volume 3A, section “Buffering of Write Combining Memory Locations” will
operate correctly.
Status: For the steppings affected, see the Summary Tables of Changes.
AH85. Fault on ENTER Instruction May Result in Unexpected Values on Stack
Frame
Problem: The ENTER instruction is used to create a procedure stack frame. Due to this erratum,
if execution of the ENTER instruction results in a fault, the dynamic storage area of the
resultant stack frame may contain unexpected values (i.e., residual stack data as a
result of processing the fault).
Implication: Data in the created stack frame may be altered following a fault on the ENTER
instruction. Please refer to "Procedure Calls For Block-Structured Languages" in the
Intel
®
64 and IA-32 Architectures Software Developer’s Manual, Vol. 1, Basic
Architecture, for information on the usage of the ENTER instructions. This erratum is
not expected to occur in ring 3. Faults are usually processed in ring 0 and stack switch
occurs when transferring to ring 0. Intel has not observed this erratum on any
commercially-available software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AH86. CPUID Reports Architectural Performance Monitoring Version 2 Is
Supported, When Only Version 1 Capabilities Are Available
Problem: CPUID leaf 0Ah reports the architectural performance monitoring version that is
available in EAX[7:0]. Due to this erratum CPUID reports the supported version as 2
instead of 1.
Implication: Software will observe an incorrect version number in CPUID.0Ah.EAX [7:0] in
comparison to which features are actually supported.
Workaround: Software should use the recommended enumeration mechanism described in the
Architectural Performance Monitoring section of the Intel
®
64 and IA-32 Architecture
Software Developer's Manual, Volume 3: System Programming Guide.
Status: For the steppings affected, see the Summary Tables of Changes.