Datasheet

Errata

Specification Update 73

AH81. A MOV Instruction from CR8 Register with 16-Bit Operand Size Will

Leave Bits 63:16 of the Destination Register Unmodified

Problem: Moves to/from control registers are supposed to ignore REW.W and the 66H (operand

size) prefix. In systems supporting Intel Virtualization Technology, when the processor

is operating in VMX non-root operation and “use TPR shadow” VM-execution control is

set to 1, a MOV instruction from CR8 with a 16 bit operand size (REX.W =0 and 66H

prefix) will only store 16 bits and leave bits 63:16 at the destination register

unmodified, instead of storing zeros in them.

Implication: Intel has not observed this erratum with any commercially available software.

Workaround: None identified.

Status: For the steppings affected, see the Summary Tables of Changes.

AH82. Debug Register May Contain Incorrect Information on a MOVSS or

POPSS Instruction Followed by SYSRET

Problem: In IA-32e mode, if a MOVSS or POPSS instruction with a debug breakpoint is followed

by the SYSRET instruction; incorrect information may exist in the Debug Status

Implication: When debugging or when developing debuggers, this behavior should be noted. This

erratum does not occur under normal usage of the MOVSS or POPSS instructions (that

is, following them with a MOV ESP instruction).

Workaround: Do not attempt to put a breakpoint on MOVSS and POPSS instructions that are

followed by a SYSRET.

Status: For the steppings affected, see the Summary Tables of Changes.

AH83. Single Step Interrupts with Floating Point Exception Pending May Be

Mishandled

Problem: In certain circumstances, when a floating point exception (#MF) is pending during

single-step execution, processing of the single-step debug exception (#DB) may be

mishandled.

Implication: When this erratum occurs, #DB will be incorrectly handled as follows:

 #DB is signaled before the pending higher priority #MF (Interrupt 16)

 #DB is generated twice on the same instruction

Workaround: None Identified

Status: For the steppings affected, see the Summary Tables of Changes.