Datasheet

Errata
72 Specification Update
AH78. Performance Monitor SSE Retired Instructions May Return Incorrect
Values
Problem: The SIMD_INST_RETIRED (Event: C7H) is used to track retired SSE instructions. Due
to this erratum, the processor may also count other types of instructions resulting in
values higher than the number of actual retired SSE instructions.
Implication: The event monitor instruction SIMD_INST_RETIRED may report count higher than
expected.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AH79. Performance Monitoring Events for L1 and L2 Miss May Not Be
Accurate
Problem: Performance monitoring events 0CBh with an event mask value of 02h or 08h
(MEM_LOAD_RETIRED.L1_LINE_MISS or MEM_LOAD_RETIRED.L2_LINE_MISS) may
under count the cache miss events.
Implication: These performance monitoring events may show a count which is lower than
expected; the amount by which the count is lower is dependent on other conditions
occurring on the same load that missed the cache.
Workaround: None Identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AH80. Store to WT Memory Data May Be Seen in Wrong Order by Two
Subsequent Loads
Problem: When data of Store to WT memory is used by two subsequent loads of one thread and
another thread performs cacheable write to the same address the first load may get
the data from external memory or L2 written by another core, while the second load
will get the data straight from the WT Store.
Implication: Software that uses WB to WT memory aliasing may violate proper store ordering.
Workaround: Do not use WB to WT aliasing.
Status: For the steppings affected, see the Summary Tables of Changes.