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Errata
Specification Update 63
AH55. Using Memory Type Aliasing with Memory Types WB/WT May Lead to
Unpredictable Behavior
Problem: Memory type aliasing occurs when a single physical page is mapped to two or more
different linear addresses, each with different memory type. Memory type aliasing
with the memory types WB and WT may cause the processor to perform incorrect
operations leading to unpredictable behavior.
Implication: Software that uses aliasing of WB and WT memory types may observe unpredictable
behavior.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
AH56. Update of Read/Write (R/W) or User/Supervisor (U/S) or Present (P)
Bits without TLB Shootdown May Cause Unexpected Processor
Behavior
Problem: Updating a page table entry by changing R/W, U/S or P bits without TLB shootdown
(as defined by the 4 step procedure in "Propagation of Page Table and Page Directory
Entry Changes to Multiple Processors" In volume 3A of the Intel
®
64 and IA-32
Architectures Software Developer’s Manual), in conjunction with a complex sequence
of internal processor micro-architectural events, may lead to unexpected processor
behavior.
Implication: This erratum may lead to livelock, shutdown or other unexpected processor behavior.
Intel has not observed this erratum with any commercially available system.
Workaround: None Identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AH57. BTS Message May Be Lost When the STPCLK# Signal Is Active
Problem: STPCLK# is asserted to enable the processor to enter a low-power state. Under some
circumstances, when STPCLK# becomes active, the BTS (Branch Trace Store)
message may be either lost and not written or written with corrupted branch address
to the Debug Store area.
Implication: BTS messages may be lost or be corrupted in the presence of STPCLK# assertions.
Workaround: None Identified.
Status: For the steppings affected, see the Summary Tables of Changes.