Datasheet
Errata
Specification Update 57
AH38. FXSAVE/FXRSTOR Instructions which Store to the End of the Segment
and Cause a Wrap to a Misaligned Base Address (Alignment <=
0x10h) May Cause FPU Instruction or Operand Pointer Corruption
Problem: If a FXSAVE/FXRSTOR instruction stores to the end of the segment causing a wrap to
a misaligned base address (alignment <= 0x10h), and one of the following conditions
is satisfied:
1. 32-bit addressing, obtained by using address-size override, when in 64-bit mode
2. 16-bit addressing in legacy or compatibility mode.
Then, depending on the wrap-around point, one of the below saved values may be
corrupted:
FPU Instruction Pointer Offset
FPU Instruction Pointer Selector
FPU Operand Pointer Selector
FPU Operand Pointer Offset
Implication: This erratum could cause FPU Instruction or Operand pointer corruption and may lead
to unexpected operations in the floating point exception handler.
Workaround: Avoid segment base misalignment and address wrap-around at the segment
boundary.
Status: For the steppings affected, see the Summary Tables of Changes.
AH39. Cache Data Access Request from One Core Hitting a Modified Line in
the L1 Data Cache of the Other Core May Cause Unpredictable System
Behavior
Problem: When request for data from Core 1 results in a L1 cache miss, the request is sent to
the L2 cache. If this request hits a modified line in the L1 data cache of Core 2, certain
internal conditions may cause incorrect data to be returned to the Core 1.
Implication: This erratum may cause unpredictable system behavior.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
AH40. PREFETCHh Instruction Execution under Some Conditions May Lead to
Processor Livelock
Problem: PREFETCHh instruction execution after a split load and dependent upon ongoing store
operations may lead to processor livelock.
Implication: Due to this erratum, the processor may livelock.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.