Datasheet

Errata
Specification Update 55
AH33. Unsynchronized Cross-Modifying Code Operations Can Cause
Unexpected Instruction Execution Results
Problem: The act of one processor, or system bus master, writing data into a currently
executing code segment of a second processor with the intent of having the second
processor execute that data as code is called cross-modifying code (XMC). XMC that
does not force the second processor to execute a synchronizing instruction, prior to
execution of the new code, is called unsynchronized XMC. Software using
unsynchronized XMC to modify the instruction byte stream of a processor can see
unexpected or unpredictable execution behavior from the processor that is executing
the modified code.
Implication: In this case, the phrase "unexpected or unpredictable execution behavior"
encompasses the generation of most of the exceptions listed in the Intel
®
64 and IA-
32 Architectures Software Developer’s Manual Volume 3: System Programming Guide,
including a General Protection Fault (GPF) or other unexpected behaviors. In the event
that unpredictable execution causes a GPF the application executing the
unsynchronized XMC operation would be terminated by the operating system.
Workaround: In order to avoid this erratum, programmers should use the XMC synchronization
algorithm as detailed in the Intel
®
64 and IA-32 Architectures Software Developer‟s
Manual Volume 3: System Programming Guide, Section: Handling Self- and Cross-
Modifying Code.
Status: Fixed. For the steppings affected, see the Summary Tables of Changes.
AH34. MSRs Actual Frequency Clock Count (IA32_APERF) or Maximum
Frequency Clock Count (IA32_MPERF) May Contain Incorrect Data
after a Machine Check Exception (MCE)
Problem: When an MCE occurs during execution of a RDMSR instruction for MSRs Actual
Frequency Clock Count (IA32_APERF) or Maximum Frequency Clock Count
(IA32_MPERF), the current and subsequent RDMSR instructions for these MSRs may
contain incorrect data.
Implication: After an MCE event, accesses to the IA32_APERF and IA32_MPERF MSRs may return
incorrect data. A subsequent reset will clear this condition.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.