Datasheet

Errata
54 Specification Update
AH31. Performance Monitoring Events for Retired Loads (CBH) and
Instructions Retired (C0H) May Not Be Accurate
Problem: The following events may be counted as instructions that contain a load by the
MEM_LOAD_RETIRED performance monitor events and may be counted as loads by
the INST_RETIRED (mask 01H) performance monitor event:
 Prefetch instructions
 x87 exceptions on FST* and FBSTP instructions
 Breakpoint matches on loads, stores, and I/O instructions
 Stores which update the A and D bits
 Stores that split across a cache line
 VMX transitions
 Any instruction fetch that misses in the ITLB
Implication: The MEM_LOAD_RETIRED and INST_RETIRED (mask 01H) performance monitor
events may count a value higher than expected. The extent to which the values are
higher than expected is determined by the frequency of the above events.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AH32. Upper 32 Bits of 'From' Address Reported through BTMs or BTSs May
Be Incorrect
Problem: When a far transfer switches the processor from 32-bit mode to IA-32e mode, the
upper 32 bits of the 'From' (source) addresses reported through the BTMs (Branch
Trace Messages) or BTSs (Branch Trace Stores) may be incorrect.
Implication: The upper 32 bits of the 'From' address debug information reported through BTMs or
BTSs may be incorrect during this transition.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.