Datasheet

Errata
Specification Update 53
AH28. EIP May Be Incorrect after Shutdown in IA-32e Mode
Problem: When the processor is going into shutdown state the upper 32 bits of the instruction
pointer may be incorrect. This may be observed if the processor is taken out of
shutdown state by NMI#.
Implication: A processor that has been taken out of the shutdown state may have an incorrect EIP.
The only software which would be affected is diagnostic software that relies on a valid
EIP.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AH29. #GP Fault Is Not Generated on Writing IA32_MISC_ENABLE [34]
When Execute Disable Is Not Supported
Problem: A #GP fault is not generated on writing to IA32_MISC_ENABLE [34] bit in a processor
which does not support Execute Disable functionality.
Implication: Writing to IA32_MISC_ENABLE [34] bit is silently ignored without generating a fault.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AH30. (E)CX May Get Incorrectly Updated When Performing Fast String REP
MOVS or Fast String REP STOS with Large Data Structures
Problem: When performing Fast String REP MOVS or REP STOS commands with data structures
[(E)CX*Data Size] larger than the supported address size structure (64 kB for 16-bit
address size and 4 GB for 32-bit address size) some addresses may be processed
more than once. After an amount of data greater than or equal to the address size
structure has been processed, external events (such as interrupts) will cause the
(E)CX registers to be increment by a value that corresponds to 64 kB for 16-bit
address size and 4 GB for 32-bit address size.
Implication: (E)CX may contain an incorrect count which may cause some of the MOVS or STOS
operations to re-execute. Intel has not observed this erratum with any commercially
available software.
Workaround: Do not use values in (E)CX that when multiplied by the data size, give values larger
than the address space size (64 kB for 16-bit address size and 4 GB for 32-bit address
size).
Status: For the steppings affected, see the Summary Tables of Changes.