Datasheet
Summary Tables of Changes
40 Specification Update
Number
Stepping
Stepping
Stepping
Plans
Errata
A-1
E-1
M-1
AH94
X
Fixed
Performance Monitoring Counter MACRO_INSTS.DECODED May
Not Count Some Decoded Instructions
AH95
X
X
X
Plan Fix
The Stack May Be Incorrect as a Result of VIP/VIF Check on
SYSEXIT and SYSRET
AH96
X
X
X
No Fix
Performance Monitoring Event SIMD_UOP_TYPE_EXEC.MUL is
Counted Incorrectly for PMULUDQ Instruction
AH97
X
X
X
No Fix
Storage of PEBS Record Delayed Following Execution of MOV SS or
STI
AH98
X
X
X
No Fix
Updating Code Page Directory Attributes without TLB Invalidation
May Result in Improper Handling of Code #PF
AH99
X
X
X
Plan Fix
Performance Monitoring Event CPU_CLK_UNHALTED.REF May Not
Count Clock Cycles According to the Processors Operating
Frequency
AH100
X
X
X
Plan Fix
Store Ordering May Be Incorrect between WC and WP Memory
Types
AH102
X
Fixed
Performance Monitoring Event BR_INST_RETIRED May Count
CPUID Instructions as Branches
AH103
X
X
X
No Fix
Performance Monitoring Event MISALIGN_MEM_REF May Over
Count
AH104
X
X
X
No Fix
A REP STOS/MOVS to a MONITOR/MWAIT Address Range May
Prevent Triggering of the Monitoring Hardware
AH105
X
Fixed
False Level One Data Cache Parity Machine-Check Exceptions
May Be Signaled
AH106
X
X
X
No Fix
A Memory Access May Get a Wrong Memory Type Following a #GP
due to WRMSR to an MTRR Mask
AH107
X
X
X
No Fix
PMI While LBR Freeze Enabled May Result in Old/Out-of-date LBR
Information
AH110
X
X
No Fix
BIST Failure after Reset
AH111
X
X
X
No Fix
Performance Monitoring Event FP_MMX_TRANS_TO_MMX May Not
Count Some Transitions
AH112
X
X
X
No Fix
Instruction Fetch May Cause a Livelock During Snoops of the L1
Data Cache
AH113
X
X
X
No Fix
Use of Memory Aliasing with Inconsistent Memory Type may
Cause a System Hang or a Machine Check Exception
AH114
X
X
X
No Fix
A WB Store Following a REP STOS/MOVS or FXSAVE May Lead to
Memory-Ordering Violations
AH116
X
X
X
No Fix
Using Memory Type Aliasing with Cacheable and WC Memory
Types May Lead to Memory Ordering Violations
AH117
X
X
X
No Fix
RSM Instruction Execution under Certain Conditions May Cause
Processor Hang or Unexpected Instruction Execution Results
AH118
X
X
X
No Fix
NMIs May Not Be Blocked by a VM-Entry Failure