Datasheet
Summary Tables of Changes
Specification Update 37
Number
Stepping
Stepping
Stepping
Plans
Errata
A-1
E-1
M-1
AH21
X
Fixed
Global Pages in the Data Translation Look-Aside Buffer (DTLB) May
Not Be Flushed by RSM instruction before Restoring the
Architectural State from SMRAM
AH22
X
Fixed
Sequential Code Fetch to Non-canonical Address May have
Nondeterministic Results
AH24
X
X
X
No Fix
REP MOVS/STOS Executing with Fast Strings Enabled and Crossing
Page Boundaries with Inconsistent Memory Types May Use an
Incorrect Data Size or Lead to Memory-Ordering Violations.
AH25
X
X
X
No Fix
Some Bus Performance Monitoring Events May Not Count Local
Events under Certain Conditions
AH26
X
X
X
No Fix
Premature Execution of a Load Operation Prior to Exception
Handler Invocation
AH27
X
X
X
No Fix
General Protection (#GP) Fault May Not Be Signaled on Data
Segment Limit Violation above 4-G Limit
AH28
X
X
X
No Fix
EIP May Be Incorrect after Shutdown in IA-32e Mode
AH29
X
X
X
No Fix
#GP Fault Is Not Generated on Writing IA32_MISC_ENABLE [34]
When Execute Disable Is Not supported
AH30
X
Fixed
(E)CX May Get Incorrectly Updated Fast String REP MOVS or Fast
String REP STOS with Large Data Structures
AH31
X
Fixed
Performance Monitoring Events for Retired Loads (CBH) and
Instructions Retired (C0H) May Not Be Accurate
AH32
X
X
X
No Fix
Upper 32 bits of „From‟ Address Reported through BTMs or BTSs
May Be Incorrect
AH33
X
Fixed
Unsynchronized Cross-Modifying Code Operations Can Cause
unexpected Instruction Execution Results
AH34
X
X
X
No Fix
MSRs Actual Frequency Clock Count (IA32_APERF) or Maximum
Frequency Clock Count (IA32_MPERF) May Contain Incorrect Data
after a Machine Check Exception (MCE)
AH35
X
X
X
No Fix
Incorrect Address Computed for Last Byte of FXSAVE/FXRSTOR
Image Leads to Partial Memory Update
AH36
X
X
X
No Fix
Split Locked Stores May Not Trigger the Monitoring Hardware
AH37
X
Fixed
REP CMPS/SCAS Operations May Terminate Early in 64-bit Mode
When RCX >= 0X100000000
AH38
X
Fixed
FXSAVE/FXRSTOR Instructions which Store to the End of the
Segment and Cause a Wrap to a Misaligned Base Address
(Alignment <=0x10h) May Cause FPU Instruction or Operand
Pointer Corruption
AH39
X
Fixed
Cache Data Access Request from One Core Hitting a Modified Line
in the L1 Data Cache of the Other Core May Cause Unpredictable
System Behavior
AH40
X
Fixed
PREFETCHh Instruction Execution under Some Conditions May
Lead to Processor Livelock