Datasheet
Summary Tables of Changes
32 Specification Update
Number
Stepping
Stepping
Stepping
Plans
ERRATA
E-1
M-1
G-2
AH60
X
X
X
No Fix
LBR, BTS, BTM May Report a Wrong Address when an
Exception/Interrupt Occurs in 64-bit Mode
AH61
X
X
X
No Fix
A Thermal Interrupt Is Not Generated when the Current
Temperature Is Invalid
AH62
X
X
X
No Fix
CMPSB, LODSB, or SCASB in 64-bit Mode with Count Greater or
Equal to 2
48
May Terminate Early
AH63
Removed Erratum
AH64
X
X
X
No Fix
Returning to Real Mode from SMM with EFLAGS.VM Set May Result
in Unpredictable System Behavior
AH65
Fixed
VMLAUNCH/VMRESUME May Not Fail When VMCS Is Programmed
to Cause VM Exit to Return to a Different Mode
AH66
X
X
X
No Fix
IRET under Certain Conditions May Cause an Unexpected
Alignment Check Exception
AH67
X
X
X
No Fix
Performance Monitoring Event FP_ASSIST May Not Be Accurate
AH68
Fixed
CPL-Qualified BTS May Report Incorrect Branch-From Instruction
Address
AH69
Fixed
PEBS Does Not Always Differentiate Between CPL-Qualified Events
AH70
X
X
X
No Fix
PMI May Be Delayed to Next PEBS Event
AH71
Fixed
PEBS Buffer Overflow Status Will Not Be Indicated Unless
IA32_DEBUGCTL[12] Is Set
AH72
X
X
X
No Fix
The BS Flag in DR6 May Be Set for Non-Single-Step #DB Exception
AH73
X
X
X
No Fix
An Asynchronous MCE during a Far Transfer May Corrupt ESP
AH74
Fixed
In Single-Stepping on Branches Mode, the BS Bit in the Pending-
Debug-Exceptions Field of the Guest State Area will be Incorrectly
Set by VM Exit on a MOV to CR8 Instruction
AH75
X
X
X
No Fix
B0-B3 Bits in DR6 May Not Be Properly Cleared after Code
Breakpoint
AH76
X
X
X
No Fix
BTM/BTS Branch-From Instruction Address May Be Incorrect for
Software Interrupts
AH77
Fixed
REP Store Instructions in a Specific Situation May Cause the
Processor to Hang
AH78
X
X
X
No Fix
Performance Monitor SSE Retired Instructions May Return
Incorrect Values
AH79
X
X
X
No Fix
Performance Monitoring Events for L1 and L2 Miss May Not Be
Accurate
AH80
X
X
X
No Fix
Store to WT Memory Data May Be Seen in Wrong Order by Two
Subsequent Loads
AH81
X
X
X
No Fix
A MOV Instruction from CR8 Register with 16 Bit Operand Size Will
Leave Bits 63:16 of the Destination Register Unmodified