Datasheet
Summary Tables of Changes
Specification Update 29
Errata for Intel
®
Core™2 Duo Processors for Platforms
Based on Mobile Intel
®
965 Express Chipset Family
Number
Stepping
Stepping
Stepping
Plans
ERRATA
E-1
M-1
G-2
AH1
X
X
X
No Fix
Writing the Local Vector Table (LVT) When an Interrupt Is Pending
May Cause an Unexpected Interrupt
AH2
X
X
X
No Fix
LOCK# Asserted During a Special Cycle Shutdown Transaction May
Unexpectedly Deassert
AH3
X
X
X
No Fix
Address Reported by Machine-Check Architecture (MCA) on Single-
bit L2 ECC Errors May Be Incorrect
AH4
X
X
X
No Fix
VERW/VERR/LSL/LAR Instructions May Unexpectedly Update the
Last Exception Record (LER) MSR
AH5
X
X
X
No Fix
DR3 Address Match on MOVD/MOVQ/MOVNTQ Memory Store
Instruction May Incorrectly Increment Performance Monitoring
Count for Saturating SIMD Instructions Retired (Event CFH)
AH6
Fixed
SYSRET May Incorrectly Clear RF (Resume Flag) in the RFLAGS
Register
AH7
X
X
X
No Fix
General Protection Fault (#GP) for Instructions Greater than 15
Bytes May Be Preempted
AH8
X
X
X
No Fix
Pending x87 FPU Exceptions (#MF) Following STI May Be Serviced
Before Higher Priority Interrupts
AH9
X
X
X
No Fix
The Processor May Report a #TS Instead of a #GP Fault
AH10
Removed Erratum
AH11
X
X
X
No Fix
A Write to an APIC Register Sometimes May Appear to Have Not
Occurred
AH12
X
X
X
No Fix
Programming the Digital Thermal Sensor (DTS) Threshold May
Cause Unexpected Thermal Interrupts
AH13
X
X
X
No Fix
Count Value for Performance-Monitoring Counter
PMH_PAGE_WALK May Be Incorrect
AH14
X
X
X
No Fix
LER MSRs May be Incorrectly Updated
AH15
X
X
X
No Fix
Performance Monitoring Events for Retired Instructions (C0H) May
Not Be Accurate
AH16
X
X
X
No Fix
Performance Monitoring Event For Number Of Reference Cycles
When The Processor Is Not Halted (3CH) Does Not Count
According To The Specification
AH17
X
X
X
No Fix
Using 2M/4M Pages When A20M# Is Asserted May Result in
Incorrect Address Translations
AH18
X
X
X
No Fix
Writing Shared Unaligned Data that Crosses a Cache Line without
Proper Semaphores or Barriers May Expose a Memory Ordering
Issue