Datasheet
Summary Tables of Changes
Specification Update 27
Number
Stepping
Stepping
Stepping
Plans
ERRATA
B-2
L-2
A-1
AH98
X
X
X
No Fix
Updating Code Page Directory Attributes without TLB
Invalidation May Result in Improper Handling of Code #PF
AH99
X
X
Plan Fix
Performance Monitoring Event CPU_CLK_UNHALTED.REF
May Not Count Clock Cycles According to the Processors
Operating Frequency
AH100
X
X
X
Plan Fix
Store Ordering May be Incorrect between WC and WP
Memory Types
AH101
X
X
Plan Fix
(E)CX May Get Incorrectly Updated When Performing Fast
String REP STOS With Large Data Structures
AH102
X
X
X
Plan Fix
Performance Monitoring Event BR_INST_RETIRED May
Count CPUID Instructions as Branches
AH103
X
X
X
No Fix
Performance Monitoring Event MISALIGN_MEM_REF May
Over Count
AH104
X
X
X
No Fix
A REP STOS/MOVS to a MONITOR/MWAIT Address Range
May Prevent Triggering of the Monitoring Hardware
AH105
X
X
X
Plan Fix
False Level One Data Cache Parity Machine-Check
Exceptions May be Signaled
AH106
X
X
X
No Fix
A Memory Access May Get a Wrong Memory Type Following
a #GP due to WRMSR to an MTRR Mask
AH107
X
X
X
No Fix
PMI While LBR Freeze Enabled May Result in Old/Out-of-
date LBR Information
AH108
X
X
Plan Fix
Overlap of an Intel
®
VT APIC Access Page in a Guest with
the DS Save Area May Lead to Unpredictable Behavior
AH109
X
X
No Fix
VTPR Write Access During Event Delivery May Cause an
APIC-Access VM Exit
AH110
No Fix
BIST Failure After Reset
AH111
X
X
X
No Fix
Performance Monitoring Event FP_MMX_TRANS_TO_MMX
May Not Count Some Transitions
AH112
X
X
X
No Fix
Instruction Fetch May Cause a Livelock During Snoops of
the L1 Data Cache
AH113
X
X
X
No Fix
Use of Memory Aliasing with Inconsistent Memory Type
may Cause a System Hang or a Machine Check Exception
AH114
X
X
X
No Fix
A WB Store Following a REP STOS/MOVS or FXSAVE May
Lead to Memory-Ordering Violations
AH115
X
X
X
No Fix
VM Exit with Exit Reason “TPR Below Threshold” Can Cause
the Blocking by MOV/POP SS and Blocking by STI Bits to
Be Cleared in the Guest Interruptibility-State Field
AH116
X
X
X
No Fix
Using Memory Type Aliasing with Cacheable and WC
Memory Types May Lead to Memory Ordering Violations
AH117
X
X
X
No Fix
RSM Instruction Execution under Certain Conditions May
Cause Processor Hang or Unexpected Instruction Execution
Results