Datasheet

Summary Tables of Changes
24 Specification Update
Number
Stepping
Stepping
Stepping
Plans
ERRATA
B-2
L-2
A-1
AH38
X
X
X
Plan Fix
FXSAVE/FXRSTOR Instructions which Store to the End of
the Segment and Cause a Wrap to a Misaligned Base
Address (Alignment <= 0x10h) May Cause FPU Instruction
or Operand Pointer Corruption
AH39
X
X
Fixed
Cache Data Access Request from One Core Hitting a
Modified Line in the L1 Data Cache of the Other Core May
Cause Unpredictable System Behavior
AH40
X
X
X
Plan Fix
PREFETCHh Instruction Execution under Some Conditions
May Lead to Processor Livelock
AH41
X
X
X
Plan Fix
PREFETCHh Instructions May Not Be Executed when
Alignment Check (AC) Is Enabled
AH42
X
X
X
Plan Fix
Upper 32 Bits of the FPU Data (Operand) Pointer in the
FXSAVE Memory Image May Be Unexpectedly All 1‟s after
FXSAVE
AH43
X
X
Fixed
Concurrent Multi-processor Writes to Non-dirty Page May
Result in Unpredictable Behavior
AH44
X
X
X
Plan Fix
Performance Monitor IDLE_DURING_DIV (18h) Count May
Not Be Accurate
AH45
X
X
X
No Fix
Values for LBR/BTS/BTM Will Be Incorrect after an Exit
from SMM
AH46
X
X
Fixed
Shutdown Condition May Disable Non-Bootstrap Processors
AH47
X
X
Fixed
SYSCALL Immediately after Changing EFLAGS.TF May Not
Behave According to the New EFLAGS.TF
AH48
X
X
X
No Fix
Code Segment Limit/Canonical Faults on RSM May be
Serviced before Higher Priority Interrupts/Exceptions and
May Push the Wrong Address Onto the Stack
AH49
X
X
X
No Fix
VM Bit Is Cleared on Second Fault Handled by Task Switch
from Virtual-8086 (VM86)
AH50
X
X
X
Plan Fix
IA32_FMASK Is Reset during an INIT
AH51
X
X
X
No Fix
An Enabled Debug Breakpoint or Single Step Trap May Be
Taken after MOV SS/POP SS Instruction if it is Followed by
an Instruction That Signals a Floating Point Exception
AH52
X
X
X
No Fix
Last Branch Records (LBR) Updates May Be Incorrect after
a Task Switch
AH53
X
X
X
No Fix
IO_SMI Indication in SMRAM State Save Area May Be Set
Incorrectly
AH54
X
X
X
No Fix
INIT Does Not Clear Global Entries in the TLB
AH55
X
X
X
Plan Fix
Using Memory Type Aliasing with Memory Types WB/WT
May Lead to Unpredictable Behavior
AH56
X
X
X
Plan Fix
Update of Read/Write (R/W) or User/Supervisor (U/S) or
Present (P) Bits without TLB Shootdown May Cause
Unexpected Processor Behavior