Datasheet
Mobile Intel
®
Celeron
®
Processor (0.18µ) in BGA2 and Micro-PGA2 Packages
Datasheet 283654-003 52
Figure 23. Pin/Ball Map - Top View
V0024-03
VCC Other VCCT VSS
Analog
Decoupling
VSS D30#D21#D23# NC NC NC D10# D14# VSSVSSNC D5# VSSVSS RESET# A33# A32# A29# VSS
D31#D29#D27#VSS
D22#
D13#VSSD18#
D9#
D11#
D7#VSS
D4#
VSS
VSS
VSS
VSSA34#
A28#
A30#VSS
D33#D35#VSS D26# D24# VSSVSSNC D20# D8#VSSD6# VSSD3#D2#BREQ0#A35# A20# A26# A31#A27#
D38#D37#D32#D28# D25# NC D16# NC D15# D17# D1#D0# VSSNC VSS VSS A24# A25# A21# VSS A22#
D45#D43#VSS D34# VREFVREF NC D19# VSSD12# VSSVSS VSSVSSVSS BERR#VREF A15# VSSA23#A19#
D42#VSS
VREF
A17#
VSSA18#A16#
D51#D49#NC NC VSSNCA13#
D47#VSS NC NC NC VSS A14#
D59#D46#NC VSS A11# A5# A10#
D53#VSS A8# A12# A4# VSS A9#
D55#D60#VSS A6# A3# A7#
D56#VSS
NC
NCBCLK
DEFER#
VSS VSS TESTLO2VSS VSSVSS VSS
DEP5# DEP6# VSSNC NC CLKREF
DEP3# VSS VSSVSS VSSRSVD LOCK#
DEP1#
D58#VSSBNR#
VSSREQ0#DRDY#
DEP2# VSS VREF BPRI# DEFER# TRDY#RS0#
BINIT# DEP0# PWRGOODREQ1#VSSREQ2#HIT#
BPM0# PRDY# REQ4#VSS REQ3# RP# RS2#
BP3#PICD1TESTLO1 HITM#VSSAP1# RSP#
BP2#VSS NC VSS DBSY#RS1# AERR#
PICD0PREQ# VSSVSSADS#AP0#
VSS
NCVSSNC
VSSVSS
NC VID2 VID0 VSS VSS
21 20 19 18 17 16 151413 1211109 8 76 5 43 21
PLL2
VSS
VSS NC VCCT VCCT VCCT VCCTVCCTVCCTVCCT VCCT VCCTVCCT VCCT VCCT
D44#D39# VCCT VCCT
VSS D48# VCCT VCCT
D61#D54#
VCCT
VCCT
VSS VSS VCCT VCCT
VSS D50# VCCT VCCT
D56#D63# VCCT VCCT
VSS
VSS
VCCT
VCCT
DEP7# D62# VCCT VCCT
VSS DEP4# VCCT VCCT VCCT VCCTVCCTVCCTVCCT VCCT VCCTVCCT VCCT VCCT
BPM1# VSS VCCT VCCT VCCT VCCTVCCTVCCTVCCT VCCT VCCTVCCT VCCT VCCT
VSS VREF VREFVSSVSSVSS VSSVSSVSSVSS VSSVCCT VCCT VCCT
VSS D41# VCCT VCCT
D57#D52# VCCT VCCT
D36#D40#
VREFVSSVSSVSS
VSSVSSVSSVSS
VSSVSSVSS
VSS
NC PICCLK NC
EDGE
CTRLP
THERM
DA
TRST# VSSBSEL0 TCKINIT#
CMOS
REF
VCCT VCCT VCCT
RSVD INTR VSS
THERM
DC
BSEL1 VSS VSSSLP#VSSSMI# VSSVCCT VCCT VCCT
NMIVSS
NC
VSSTDO
VSS
IGNNE#
FERR#STPCLK#
VSS
FLUSH#
VCCT
VCCT
VCCT
RTT
IMPEDP
CMOS
REF
TESTHI VSSNC TMSTDINC NC A20M# IERR#VCCT VCCT VCCT
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
A
C
A
D
VSS VCC VSS VCC VSS VCC
VCC VSS VCC VSS VCC VSS
VSS
VCC
VSS VCC
VSS
VCC VSS VCC VSS VCC
VSS VCC VSS VCC VSS VCC
VCC VSS VCC VSS VCC VSS
VSS
VCC
VSS VCC
VSS
VCC
VCC VSS VCC VSS VCC VSS
VCC VSS VCC VSS VCC VSS
VSS VCC VSS VCC VSS VCC
VCC
VSS
VSS VCC
VCC VSS
VSS
VCC
VCC VSS
VSS VCC
VCC VSS
VSS
VCC
VCC VSS
VCC VSS
VSS VCC
VSS VCC
VCC VSS
VSS VCC
VCC VSS
VSS VCC
VCC VSS
VSS VCC
VCC VSS
VCC VSS
VSS VCC
VID4
VID3
VID1
PLL1
VCC
2
NOTES:
1. In order to implement VID on the BGA2 package, some VID[4:0] balls may be depopulated. However, on
the Micro-PGA2 package, VID[4:0] pins are not depopulated.
2. For any of the following conditions, the pin/ball P1 must be connected to Vcc:
• All processors with a nominal core operating voltage less than 1.35V or greater than 1.60V
• All processors based on any new steppings following C-step
For all other processors based on A2/B0/C0 stepping, the pin/ball P1 can be connected to either Vcc or
Vcct.