Datasheet

Mobile Intel
®
Celeron
®
Processor (0.18µ) in BGA2 and Micro-PGA2 Packages
283654-003 Datasheet 43
Figure 17. High to Low, GTL+ Receiver Ringback Tolerance
V
REF,max
+0.2V
Time
V
REF,min
-0.2V
V
REF,min
V
start
Clock
V
IL,BCLK
V
IH,BCLK
V0014-02
τ
δ
ρ
φ
α
Table 25. GTL+ Signal Group Overshoot/Undershoot Tolerance at the Processor Core
1, 4, 5
Overshoot Amplitude
2
Undershoot Amplitude
3
Allowed Pulse Duration
2.0V -0.35V 0.35 ns
1.9V -0.25V 1.2 ns
1.8V -0.15V 4.3 ns
NOTES:
1. Under no circumstances should the GTL+ signal voltage ever exceed 2.0V maximum with respect to
ground or -2.0V minimum with respect to V
CCT
(i.e., V
CCT
- 2.0V) under operating conditions.
2. Ringbacks below V
CCT
cannot be subtracted from overshoots. Lesser undershoot does not allocate longer
or larger overshoot.
3. Ringbacks above ground cannot be subtracted from undershoots. Lesser overshoot does not allocate
longer or larger undershoot.
4. System designers are encouraged to follow Intel provided GTL+ layout guidelines.
5. All values are specified by design characterization and are not tested.