Datasheet

Mobile Intel
®
Celeron
®
Processor (0.18µ) in BGA2 and Micro-PGA2 Packages
Datasheet 283654-003 36
Figure 9. Cold/Warm Reset and Configuration Timings
BCLK
RESET#
Configuration
(A[15:5], BREQ0#,
FLUSH#, INIT#,
PICD0)
T
v
T
x
T
t
T
u
T
w
Valid
D0006-01
NOTES:
T
t
= T9 (GTL+ Input Hold Time)
T
u
= T8 (GTL+ Input Setup Time)
T
v
= T10 (RESET# Pulse Width)
T18 (RESET#/PWRGOOD Setup Time)
T
w
= T16 (Reset Configuration Signals (A[15:5]#, BREQ0#, FLUSH#, INIT#, PICD0) Setup Time)
T
x
= T17 (Reset Configuration Signals (A[15:5]#, BREQ0#, FLUSH#, INIT#, PICD0) Hold Time)
Figure 10. Power-on Reset Timings
BCLK
PWRGOOD
RESET#
T
a
T
b
V ,
CC
V
REF
V ,
CCT,
V
IL25,max
V
IH25,min
D0007-01
NOTES:
T
a
= T15 (PWRGOOD Inactive Pulse Width)
T
b
= T10 (RESET# Pulse Width)