Datasheet

Mobile Intel
®
Celeron
®
Processor (0.18µ) in BGA2 and Micro-PGA2 Packages
283654-003 Datasheet 35
Figure 7. Valid Delay Timings
CLK
Signal
T
X
T
x
T
PW
VValid Valid
D0004-00
NOTES:
T
x
= T7, T11, T29 (Valid Delay)
T
pw
= T14, T14B (Pulse Width)
V = V
REF
for GTL+ signal group; 0.75V for CMOS, Open-drain, APIC, and TAP signal groups
Figure 8. Setup and Hold Timings
CLK
S
ignal
VValid
T
h
Ts
D0005-00
NOTES:
T
s
= T 8, T12, T27 (Setup Time)
T
h
= T9, T13, T28 (Hold Time)
V = V
REF
for GTL+ signals; 0.75V for CMOS, APIC, and TAP signals