Datasheet

Mobile Intel
®
Celeron
®
Processor (0.18µ) in BGA2 and Micro-PGA2 Packages
283654-003 Datasheet 33
Table 21. Stop Grant/Sleep/Deep Sleep AC Specifications
T
J
= 0°C to 100°C; T
J
= 5°C to 100°C for Vcc = 1.15V; V
CC
= 1.10V ±80 mV or 1.15V ±80 mV or 1.35V
±100 mV or 1.60V ±115; V
CCT
= 1.50V ±115 mV
Symbol Parameter Min Max Unit Figure
T50 SLP# Signal Hold Time from Stop Grant Cycle Completion 100 BCLKs Figure 14
T51 SLP# Assertion to Input Signals Stable 0 ns Figure 14
T52 SLP# Assertion to Clock Stop 10 BCLKs Figure 14
T54 SLP# Hold Time from PLL Lock 0 ns Figure 14
T55 STPCLK# Hold Time from SLP# Deassertion 10 BCLKs Figure 14
T56 Input Signal Hold Time from SLP# Deassertion 10 BCLKs Figure 14
NOTE: Input signals other than RESET# must be held constant in the Sleep state. The BCLK Settling Time
specification (T60) applies to Deep Sleep state exit under all conditions.