Datasheet

Mobile Intel
®
Celeron
®
Processor (0.18µ) in BGA2 and Micro-PGA2 Packages
283654-003 Datasheet 31
Table 17. Reset Configuration AC Specifications
T
J
= 0°C to 100°C; T
J
= 5°C to 100°C for Vcc = 1.15V; V
CC
= 1.10V ±80 mV or 1.15V ±80 mV or 1.35V ±100
mV or 1.60V ±115; V
CCT
= 1.50V ±115 mV
Symbol Parameter Min Max Unit Figure Notes
T16 Reset Configuration Signals (A[15:5]#, BREQ0#,
FLUSH#, INIT#, PICD0) Setup Time
4 BCLKs
Figure 8.
Figure 9
Before
deassertion of
RESET#
T17 Reset Configuration Signals (A[15:5]#, BREQ0#,
FLUSH#, INIT#, PICD0) Hold Time
2 20 BCLKs
Figure 8.
Figure 9
After clock that
deasserts
RESET#
T18 RESET#/PWRGOOD Setup Time 1 ms Figure 10 Before
deassertion of
RESET#
1
Table 18. APIC Bus Signal AC Specifications
1
T
J
= 0°C to 100°C; T
J
= 5°C to 100°C for Vcc = 1.15V; V
CC
= 1.10V ±80 mV or 1.15V ±80 mV or 1.35V ±100
mV or 1.60V ±115; V
CCT
= 1.50V ±115 mV
Symbol Parameter Min Max Unit Figure Notes
T21 PICCLK Frequency 2 33.3 MHz Note 2
T22 PICCLK Period 30 500 ns Figure 5
T23 PICCLK High Time 10.5 ns Figure 5 at>1.7V
T24 PICCLK Low Time 10.5 ns Figure 5 at<0.7V
T25 PICCLK Rise Time 0.25 3.0 ns Figure 5 (0.7V – 1.7V)
T26 PICCLK Fall Time 0.25 3.0 ns Figure 5 (1.7V – 0.7V)
T27 PICD[1:0] Setup Time 8.0 ns Figure 8 Note 3
T28 PICD[1:0] Hold Time 2.5 ns Figure 8 Note 3
T29 PICD[1:0] Valid Delay 1.5 10.0 ns Figure 7 Notes 3, 4, 5
NOTES:
1. All AC timings for APIC signals are referenced to the PICCLK rising edge at 1.25V. All CMOS signals are
referenced at 0.75V.
2. The minimum frequency is 2 MHz when PICD0 is at 1.5V at reset. If PICD0 is strapped to V
SS
at reset then
the minimum frequency is 0 MHz.
3. Referenced to PICCLK Rising Edge.
4. For Open-drain signals, Valid Delay is synonymous with Float Delay.
5. Valid delay timings for these signals are specified into 150Ω to 1.5V and 0 pF of external load. For real
system timings these specifications must be derated for external capacitance at 105 ps/pF.