Datasheet

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Mobile Intel

Celeron

Processor

(0.18µ) in BGA2 and Micro-PGA2

Packages

at 900 MHz, 850 MHz, 800 MHz, 750 MHz, 700 MHz, 650 MHz,

600 MHz, 550 MHz, 500 MHz, 450 MHz, Low-voltage 600 MHz,

Low-voltage 500 MHz, Low-voltage 400A MHz, and Ultra

Low-voltage 600 MHz, Ultra Low-voltage 500 MHz

Datasheet

October 2001

Order Number: 283654-003

Summary of content (80 pages)

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R Mobile Intel® Celeron® Processor (0.
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® ® Mobile Intel Celeron Processor (0.18µ) in BGA2 and Micro-PGA2 Packages Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document.
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® ® Mobile Intel Celeron Processor (0.18µ) in BGA2 and Micro-PGA2 Packages Mobile Intel® Celeron® Processor (0.18µ) in BGA2 and Micro-PGA2 Packages Product Features ! ! 283654-003 Processor core/bus speeds: ! 900/100 MHz at 1.7V 850/100 MHz at 1.6V 800/100 MHz at 1.6V 750/100 MHz at 1.6V 700/100 MHz at 1.6V 650/100 MHz at 1.6V 600/100 MHz at 1.6V ! 550/100 MHz at 1.6V 500/100 MHz at 1.6V 450/100 MHz at 1.6V 600/100 MHz at 1.35V ! 500/100 MHz at 1.35V 400A/100 MHz at 1.35V 600/100 MHz at 1.
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® ® Mobile Intel Celeron Processor (0.18µ) in BGA2 and Micro-PGA2 Packages Contents 1. Introduction.....................................................................................................................................9 1.1 1.2 1.3 2. Mobile Intel Celeron Processor Features ..................................................................................12 2.1 2.2 2.3 2.4 3. 3.2 3.3 3.4 3.5 3.6 Processor System Signals ...............................................................
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® ® Mobile Intel Celeron Processor (0.18µ) in BGA2 and Micro-PGA2 Packages 4.2 4.3 5. Mechanical Specifications...........................................................................................................46 5.1 5.2 5.3 6. Thermal Diode ......................................................................................................60 Processor Initialization and Configuration................................................................................61 7.1 7.2 8.
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® ® Mobile Intel Celeron Processor (0.18µ) in BGA2 and Micro-PGA2 Packages Figures Figure 1. Signal Groups of a Mobile Intel Celeron Processor/440MX Chipset - Based System .................................................................................................................9 Figure 2. Clock Control States ..........................................................................................14 Figure 3. Vcc Ramp Rate Requirement ..............................................................
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® ® Mobile Intel Celeron Processor (0.18µ) in BGA2 and Micro-PGA2 Packages Tables Table 1. New BGA2/Micro-PGA2 Signals .........................................................................12 Table 2. Removed BGA1/µPGA1 Signals .........................................................................13 Table 3. Clock State Characteristics .................................................................................16 Table 4. Mobile Intel Celeron Processor CPUID....................................
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® ® Mobile Intel Celeron Processor (0.18µ) in BGA2 and Micro-PGA2 Packages Revision History Date Revision Number April 2000 N/A Initial release Updates June 2000 N/A Revision 2.0 updates include: • • • • • • September 2000 N/A Revision 3.
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® ® Mobile Intel Celeron Processor (0.18µ) in BGA2 and Micro-PGA2 Packages 1. Introduction The mobile Intel Celeron processor is offered at 900 MHz, 850 MHz, 800 MHz, 750 MHz, 700 MHz, 650 MHz, 600 MHz, 550 MHz, 500 MHz, 450 MHz, low voltage 600 MHz, low voltage 500 MHz, low voltage 400A MHz, ultra low voltage 600 MHz, and ultra low voltage 500 MHz with a system bus speed of 100 MHz.
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® ® Mobile Intel Celeron Processor (0.18µ) in BGA2 and Micro-PGA2 Packages 1.1 Overview • • • • • • 1.
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® ® Mobile Intel Celeron Processor (0.18µ) in BGA2 and Micro-PGA2 Packages 1.
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® ® Mobile Intel Celeron Processor (0.18µ) in BGA2 and Micro-PGA2 Packages 2. Mobile Intel Celeron Processor Features 2.1 New Features in the Mobile Intel Celeron Processor 2.1.1 On-die GTL+ Termination The termination resistors for the GTL+ system bus are integrated onto the processor die. The RESET# signal does not have on-die termination and requires an external 56.2Ω ±1% terminating resistor. 2.1.
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® ® Mobile Intel Celeron Processor (0.18µ) in BGA2 and Micro-PGA2 Packages Table 2. Removed BGA1/µPGA1 Signals Signals Purpose EDGECTRLN GTL+ output buffer control BSEL 100/66 MHz processor system bus speed selection 2.2 Power Management 2.2.1 Clock Control Architecture The mobile Intel Celeron processor clock control architecture (Figure 2) has been optimized for leading edge deep green desktop and mobile computer designs.
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® ® Mobile Intel Celeron Processor (0.18µ) in BGA2 and Micro-PGA2 Packages The SMI# interrupt is recognized in the Auto Halt state. The return from the System Management Interrupt (SMI) handler can be to either the Normal state or the Auto Halt state. See the Intel® Architecture Software Developer’s Manual, Volume III: System Programmer’s Guide for more information. No Halt bus cycle is issued when returning to the Auto Halt state from the System Management Mode (SMM).
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® ® Mobile Intel Celeron Processor (0.18µ) in BGA2 and Micro-PGA2 Packages The processor will return to the Stop Grant state after the completion of a BINIT# bus initialization unless STPCLK# has been deasserted. RESET# assertion will cause the processor to immediately initialize itself, but the processor will stay in the Stop Grant state after initialization until STPCLK# is deasserted. A transition to the Sleep state can be made by the assertion of the SLP# signal.
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® ® Mobile Intel Celeron Processor (0.18µ) in BGA2 and Micro-PGA2 Packages The processor can be reset by the RESET# signal while in the Sleep state. If RESET# is driven active while the processor is in the Sleep state then SLP# and STPCLK# must immediately be driven inactive to ensure that the processor correctly initializes itself. Input signals (other than RESET#) may not change while the processor is in the Sleep state or transitioning into or out of the Sleep state.
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® ® Mobile Intel Celeron Processor (0.18µ) in BGA2 and Micro-PGA2 Packages counter and the performance monitor counters are not guaranteed to count in the Quick Start or Sleep states. The local APIC timer and performance monitor counter interrupts should be disabled before entering the Deep Sleep state or the resulting behavior will be unpredictable. 2.3 GTL+ Signals The mobile Intel Celeron processor system bus signals use a variation of the low-voltage swing GTL signaling technology.
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® ® Mobile Intel Celeron Processor (0.18µ) in BGA2 and Micro-PGA2 Packages 3. Electrical Specifications 3.1 Processor System Signals Table 6 lists the processor system signals by type. All GTL+ signals are synchronous with the BCLK signal. All TAP signals are synchronous with the TCK signal except TRST#. All CMOS input signals can be applied asynchronously. Table 6.
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® ® Mobile Intel Celeron Processor (0.18µ) in BGA2 and Micro-PGA2 Packages Table 7. Recommended Resistors for Mobile Intel Celeron Processor Signals Recommended Resistor Value (Ω Ω) Mobile Intel Celeron Processor Signal 1, 2 3 10 pull-down BREQ0# 56.2 pull-up RESET# 4 150 pull-up PICD[1:0], TDI, TDO 270 pull-up SMI# 680 pull-up STPCLK# 1K pull-up INIT#, TCK, TMS 1K pull-down TRST# 1.5K pull-up A20M#, FERR#, FLUSH#, IERR#, IGNNE#, LINT0/INTR, LINT1/NMI, PREQ#, PWRGOOD, SLP# NOTES: 1.
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® ® Mobile Intel Celeron Processor (0.18µ) in BGA2 and Micro-PGA2 Packages range that the mobile Intel Celeron processor can tolerate. Multiple copies of TMS and TRST# must be provided, one for each voltage level. A Debug Port and connector may be placed at the start and end of the JTAG chain containing the processor, with TDI to the first component coming from the Debug Port and TDO from the last component going to the Debug Port.
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® ® Mobile Intel Celeron Processor (0.18µ) in BGA2 and Micro-PGA2 Packages These input buffers have no internal pull-up or pull-down resistors and system logic can use CMOS or Open-drain drivers to drive them. The Open-drain output signals have open drain drivers and external pull-up resistors are required. One of the two output signals (IERR#) is a catastrophic error indicator and is tri-stated (and pulled-up) when the processor is functioning normally.
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® ® Mobile Intel Celeron Processor (0.18µ) in BGA2 and Micro-PGA2 Packages Figure 4. PLL RLC Filter L1 PLL1 VCCT C1 PLL2 3.3 R1 V0027-01 System Bus Clock and Processor Clocking The 2.5-V BCLK clock input directly controls the operating speed of the system bus interface. All system bus timing parameters are specified with respect to the rising edge of the BCLK input. The mobile Intel Celeron processor core frequency is a multiple of the BCLK frequency.
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® ® Mobile Intel Celeron Processor (0.18µ) in BGA2 and Micro-PGA2 Packages Table 8. Mobile Intel Celeron Processor Absolute Maximum Ratings Symbol Parameter Min Max Unit Notes TStorage Storage Temperature –40 85 °C VCC(Abs) Supply Voltage with respect to VSS –0.5 2.1 V Note 1 VCCT System Bus Buffer Voltage with respect to VSS –0.3 2.1 V VIN GTL System Bus Buffer DC Input Voltage with respect to VSS –0.3 2.
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® ® Mobile Intel Celeron Processor (0.18µ) in BGA2 and Micro-PGA2 Packages 3.5 DC Specifications Table 9 through Table 12 lists the DC specifications for the mobile Intel Celeron processor. Specifications are valid only while meeting specifications for junction temperature, clock frequency, and input voltages. Care should be taken to read all notes associated with each parameter. 1 Table 9. Mobile Intel Celeron Processor Power Specifications TJ = 0°C to 100°C; TJ = 5°C to 100°C for Vcc = 1.
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® ® Mobile Intel Celeron Processor (0.18µ) in BGA2 and Micro-PGA2 Packages ICC,DSLP dICC/dt at 1.10V (for 500 MHz, 600 MHz) at 1.15V (for 600 MHz) at 1.35V (for 400A MHz, 500 MHz, 600 MHz) at 1.60V (for 450 MHz, 500 MHz, 550 MHz, 600 MHz, 650 MHz) at 1.60V (for 700 MHz, 750 MHz) at 1.60V (for 800 MHz, 850 MHz) at 1.70V (for 900 MHz) Processor Deep Sleep Leakage current at 1.10V (for 500 MHz, 600 MHz) at 1.15V (for 600 MHz) at 1.35V (for 400A MHz, 500 MHz, 600 MHz) at 1.
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® ® Mobile Intel Celeron Processor (0.18µ) in BGA2 and Micro-PGA2 Packages Table 11. GTL+ Bus DC Specifications TJ = 0°C to 100°C; TJ = 5°C to 100°C for Vcc = 1.15V; VCC = 1.10V ±80 mV or 1.15V ±80 mV or 1.35V ±100 mV or 1.60V ±115; VCCT = 1.50V ±115 mV Symbol Parameter Min Typ Max Unit Notes VCCT Bus Termination Voltage 1.385 1.5 1.
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® ® Mobile Intel Celeron Processor (0.18µ) in BGA2 and Micro-PGA2 Packages Table 12. Clock, APIC, TAP, CMOS, and Open-drain Signal Group DC Specifications TJ = 0°C to 100°C; TJ = 5°C to 100°C for Vcc = 1.15V; VCC = 1.10V ±80 mV or 1.15V ±80 mV or 1.35V ±100 mV or 1.60V ±115; VCCT = 1.50V ±115 mV Symbol Parameter Min Max Unit Notes VIL15 Input Low Voltage, 1.5V CMOS –0.15 VCMOSREFmin – 200 mV V VIL25 Input Low Voltage, 2.5V CMOS –0.3 0.7 V Notes 1, 2 VIL33 Input Low Voltage, 3.3V CMOS –0.
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® ® Mobile Intel Celeron Processor (0.18µ) in BGA2 and Micro-PGA2 Packages 3.6 AC Specifications 3.6.1 System Bus, Clock, APIC, TAP, CMOS, and Open-drain AC Specifications Table 13 through Table 21 provide AC specifications associated with the mobile Intel Celeron processor.
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® ® Mobile Intel Celeron Processor (0.18µ) in BGA2 and Micro-PGA2 Packages Table 14. Valid Mobile Intel Celeron Processor Frequencies TJ = 0°C to 100°C; TJ = 5°C to 100°C for Vcc = 1.15V; VCC = 1.10V ±80 mV or 1.15V ±80 mV or 1.35V ±100 mV or 1.60V ±115; VCCT = 1.50V ±115 mV BCLK Frequency (MHz) Frequency Multiplier Core Frequency (MHz) Power-on Configuration bits [27, 25:22] 100 4.0 400A 0, 0010 100 4.5 450 0, 0110 100 5.0 500 0, 0000 100 5.5 550 0, 0100 100 6.
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® ® Mobile Intel Celeron Processor (0.18µ) in BGA2 and Micro-PGA2 Packages Table 16. CMOS and Open-drain Signal Groups AC Specifications 1, 2 TJ = 0°C to 100°C; TJ = 5°C to 100°C for Vcc = 1.15V; VCC = 1.10V ±80 mV or 1.15V ±80 mV or 1.35V ±100 mV or 1.60V ±115; VCCT = 1.50V ±115 mV Symbol Parameter Min Max Unit Figure Notes T14 1.
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® ® Mobile Intel Celeron Processor (0.18µ) in BGA2 and Micro-PGA2 Packages Table 17. Reset Configuration AC Specifications TJ = 0°C to 100°C; TJ = 5°C to 100°C for Vcc = 1.15V; VCC = 1.10V ±80 mV or 1.15V ±80 mV or 1.35V ±100 mV or 1.60V ±115; VCCT = 1.
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® ® Mobile Intel Celeron Processor (0.18µ) in BGA2 and Micro-PGA2 Packages 1 Table 19. TAP Signal AC Specifications TJ = 0°C to 100°C; TJ = 5°C to 100°C for Vcc = 1.15V; VCC = 1.10V ±80 mV or 1.15V ±80 mV or 1.35V ±100 mV or 1.60V ±115; VCCT = 1.50V ±115 mV Symbol Parameter Min Max T30 TCK Frequency — 16.67 MHz Unit Figure — Notes T31 TCK Period 60 ns Figure 5 T32 TCK High Time 25.0 ns Figure 5 ≥ 1.2V, Note 2 T33 TCK Low Time 25.0 ns Figure 5 ≤ 0.
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® ® Mobile Intel Celeron Processor (0.18µ) in BGA2 and Micro-PGA2 Packages Table 21. Stop Grant/Sleep/Deep Sleep AC Specifications TJ = 0°C to 100°C; TJ = 5°C to 100°C for Vcc = 1.15V; VCC = 1.10V ±80 mV or 1.15V ±80 mV or 1.35V ±100 mV or 1.60V ±115; VCCT = 1.
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® ® Mobile Intel Celeron Processor (0.18µ) in BGA2 and Micro-PGA2 Packages Figure 5 through Figure 14 are to be used in conjunction with Table 13 through Table 21. Figure 5. PICCLK/TCK Clock Timing Waveform Th Tr VH CLK VTRIP VL Tf Tl Tp D0003-01 NOTES: Tr Tf Th Tl Tp VL VH = T34, T25 (Rise Time) = T35, T26 (Fall Time) = T32, T23 (High Time) = T33, T24 (Low Time) = T31, T22 (Period) VTRIP = 1.25V for PICCLK; 0.75V for TCK = 0.7V for PICCLK; 0.6V for TCK = 1.7V for PICCLK; 1.2V for TCK Figure 6.
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® ® Mobile Intel Celeron Processor (0.18µ) in BGA2 and Micro-PGA2 Packages Figure 7. Valid Delay Timings CLK TX Tx V Signal Valid Valid TPW D0004-00 NOTES: Tx V = T7, T11, T29 (Valid Delay) Tpw = T14, T14B (Pulse Width) = VREF for GTL+ signal group; 0.75V for CMOS, Open-drain, APIC, and TAP signal groups Figure 8. Setup and Hold Timings CLK Ts V Th Valid Signal D0005-00 NOTES: Ts Th V 283654-003 = = = T 8, T12, T27 (Setup Time) T9, T13, T28 (Hold Time) VREF for GTL+ signals; 0.
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® ® Mobile Intel Celeron Processor (0.18µ) in BGA2 and Micro-PGA2 Packages Figure 9.
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® ® Mobile Intel Celeron Processor (0.18µ) in BGA2 and Micro-PGA2 Packages Figure 11. Test Timings (Boundary Scan) TCK Tv Tw 0.
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® ® Mobile Intel Celeron Processor (0.18µ) in BGA2 and Micro-PGA2 Packages Figure 13.
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® ® Mobile Intel Celeron Processor (0.18µ) in BGA2 and Micro-PGA2 Packages Figure 14.
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® ® Mobile Intel Celeron Processor (0.18µ) in BGA2 and Micro-PGA2 Packages 4. System Signal Simulations Many scenarios have been simulated to generate a set of GTL+ processor system bus layout guidelines, which are available in the Mobile Pentium® III Processor GTL+ System Bus Layout Guideline. Systems must be simulated using the IBIS model to determine if they are compliant with this specification. 4.
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® ® Mobile Intel Celeron Processor (0.18µ) in BGA2 and Micro-PGA2 Packages Figure 15. BCLK/PICCLK Generic Clock Waveform V3max V4 V2 V1 V5 V3min V0012-01 4.2 GTL+ AC Signal Quality Specifications Table 24, Figure 16, and Figure 17 illustrate the GTL+ signal quality specifications for the mobile Intel Celeron processor. Refer to the Pentium® II Processor Developer’s Manual for the GTL+ buffer specification.
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® ® Mobile Intel Celeron Processor (0.18µ) in BGA2 and Micro-PGA2 Packages Table 24. GTL+ Signal Group Ringback Specification Symbol Parameter Min Unit Figure Notes α Overshoot 100 mV Figure 16, Figure 17 Notes 1, 2 τ Minimum Time at High 0.
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® ® Mobile Intel Celeron Processor (0.18µ) in BGA2 and Micro-PGA2 Packages Figure 17. High to Low, GTL+ Receiver Ringback Tolerance VIH,BCLK Vstart δ VREF,max+0.2V ρ VREF,min φ VREF,min-0.2V α VIL,BCLK τ Clock V0014-02 Time Table 25. GTL+ Signal Group Overshoot/Undershoot Tolerance at the Processor Core 1, 4, 5 Overshoot Amplitude 2 Undershoot Amplitude 3 Allowed Pulse Duration 2.0V -0.35V 0.35 ns 1.9V -0.25V 1.2 ns 1.8V -0.15V 4.3 ns NOTES: 1.
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® ® Mobile Intel Celeron Processor (0.18µ) in BGA2 and Micro-PGA2 Packages Figure 18. Maximum Acceptable Overshoot/Undershoot Waveform Time dependant Overshoot 2.0V Max 1.9V 1.8V VCCT α β χ α β χ Vss -.15V -.25V -.35V Min Time dependant NOTE: 4.3 The total overshoot/undershoot budget for one clock cycle is fully consumed by the α, β, or χ waveforms.
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® ® Mobile Intel Celeron Processor (0.18µ) in BGA2 and Micro-PGA2 Packages Table 26. Non-GTL+ Signal Group Overshoot/Undershoot Tolerance at the Processor Core Overshoot Amplitude 2 Undershoot Amplitude 3 Allowed Pulse Duration 2.1V -0.45V 0.45 ns 2.0V -0.35V 1.5 ns 1.9V -0.25V 5.0 ns 1.8V -0.15V 17 ns 1, 4, 5 NOTES: 1. Under no circumstances should the non-GTL+ signal voltage ever exceed 2.1V maximum with respect to ground or -2.1V minimum with respect to VCCT (i.e., VCCT - 2.
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® ® Mobile Intel Celeron Processor (0.18µ) in BGA2 and Micro-PGA2 Packages 5. Mechanical Specifications 5.1 Surface-mount BGA2 Package Dimensions The mobile Intel Celeron processor is packaged in a PBGA-B495 package (also known as BGA2) with the back of the processor die exposed on top. Unlike previous mobile processors with exposed die, the back of the mobile Intel Celeron processor die may be polished and very smooth.
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® ® Mobile Intel Celeron Processor (0.18µ) in BGA2 and Micro-PGA2 Packages Figure 19. Surface-mount BGA2 Package - Top and Side View E1 D1 NOTE: 283654-003 All dimensions are in millimeters. Dimensions in figure are for reference only, See Table 27 for specifications.
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® ® Mobile Intel Celeron Processor (0.18µ) in BGA2 and Micro-PGA2 Packages Figure 20. Surface-mount BGA2 Package - Bottom View NOTE: All dimensions are in millimeters. Dimensions in figure are for reference only. See Table 27 for specifications. 5.2 Socketable Micro-PGA2 Package Dimensions The mobile Intel Celeron processor is also packaged in a PPGA-B495 package (also known as Micro-PGA2) with the back of the processor die exposed on top.
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® ® Mobile Intel Celeron Processor (0.18µ) in BGA2 and Micro-PGA2 Packages Table 28. Socketable Micro-PGA2 Package Specification Symbol 283654-003 Parameter Min Max Unit A Overall Height, top of die to seating plane of interposer 3.13 A1 Pin Length 1.25 REF 3.73 mm A2 Die Height 0.854 REF mm B Pin Diameter 0.30 REF mm D2 Package Width D Die Substrate Width D1 Die Width E2 Package Length E Die Substrate Length E1 Die Length mm 28.27 REF 27.
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® ® Mobile Intel Celeron Processor (0.18µ) in BGA2 and Micro-PGA2 Packages Figure 21. Socketable Micro-PGA2 Package - Top and Side View E1 D1 NOTE: 50 All dimensions are in millimeters. Dimensions in figure are for reference only. See Table 28 for specifications.
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® ® Mobile Intel Celeron Processor (0.18µ) in BGA2 and Micro-PGA2 Packages Figure 22. Socketable Micro-PGA2 Package - Bottom View NOTE: 5.3 All dimensions are in millimeters. Dimensions in figure are for reference only. See Table 28 for specifications. Signal Listings Figure 23 is a top-side view of the ball or pin map of the mobile Intel Celeron processor with the voltage balls/pins called out. Table 29 lists the signals in ball/pin number order. Table 30 lists the signals in signal name order.
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® ® Mobile Intel Celeron Processor (0.18µ) in BGA2 and Micro-PGA2 Packages Figure 23.
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® ® Mobile Intel Celeron Processor (0.18µ) in BGA2 and Micro-PGA2 Packages Table 29. Signal Listing in Order by Pin/Ball Number 283654-003 No. Signal Name No. Signal Name No. Signal Name No.
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® ® Mobile Intel Celeron Processor (0.18µ) in BGA2 and Micro-PGA2 Packages 54 No. Signal Name No. Signal Name No. Signal Name No.
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® ® Mobile Intel Celeron Processor (0.18µ) in BGA2 and Micro-PGA2 Packages 283654-003 No. Signal Name No. Signal Name No. Signal Name No.
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® ® Mobile Intel Celeron Processor (0.18µ) in BGA2 and Micro-PGA2 Packages Table 30. Signal Listing in Order by Signal Name No. 56 Signal Name Signal Buffer Type No. Signal Name Signal Buffer Type L3 A3# GTL+ I/O AA21 BP2# GTL+ I/O K3 A4# GTL+ I/O Y21 BP3# GTL+ I/O J2 A5# GTL+ I/O W21 BPM0# GTL+ I/O L4 A6# GTL+ I/O W19 BPM1# GTL+ I/O L1 A7# GTL+ I/O U4 BPRI# GTL+ Input K5 A8# GTL+ I/O C6 BREQ0# GTL+ I/O K1 A9# GTL+ I/O AA12 BSEL0 3.
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® ® Mobile Intel Celeron Processor (0.18µ) in BGA2 and Micro-PGA2 Packages 283654-003 No. Signal Name Signal Buffer Type No. Signal Name Signal Buffer Type B21 D31# GTL+ I/O T1 DRDY# GTL+ I/O D19 D32# GTL+ I/O AA16 EDGECTRLP GTL+ Control C21 D33# GTL+ I/O AC12 FERR# 1.5V Open Drain Output E18 D34# GTL+ I/O AC9 FLUSH# 1.5V CMOS Input C20 D35# GTL+ I/O R2 RSVD 1.
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® ® Mobile Intel Celeron Processor (0.18µ) in BGA2 and Micro-PGA2 Packages No. Signal Name Signal Buffer Type No.
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® ® Mobile Intel Celeron Processor (0.18µ) in BGA2 and Micro-PGA2 Packages 6. Thermal Specifications This chapter provides needed data for designing a thermal solution. The mobile Intel Celeron processor is either a surface mount PBGA-B495 package or a socketable PPGA-B495 package with the back of the processor die exposed and has a specified operational junction temperature (TJ) limit. In order to achieve proper cooling of the processor, a thermal solution (e.g.
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® ® Mobile Intel Celeron Processor (0.18µ) in BGA2 and Micro-PGA2 Packages normal operating conditions at nominal voltages. TDPTYP power is lower than TDPMAX. Contact your Intel Field Sales Representative for further information. 6.1 Thermal Diode The mobile Intel Celeron processor has an on-die thermal diode that can be used to monitor the die temperature(TJ).
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® ® Mobile Intel Celeron Processor (0.18µ) in BGA2 and Micro-PGA2 Packages 7. Processor Initialization and Configuration 7.1 Description The mobile Intel Celeron processor has some configuration options that are determined by hardware and some that are determined by software. The processor samples its hardware configuration at reset on the active-to-inactive transition of RESET#.
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® ® Mobile Intel Celeron Processor (0.18µ) in BGA2 and Micro-PGA2 Packages Configuration register. Table 14 shows the 5-bit codes in the Power-on Configuration register and their corresponding bus ratios.
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® ® Mobile Intel Celeron Processor (0.18µ) in BGA2 and Micro-PGA2 Packages 8. Processor Interface 8.1 Alphabetical Signal Reference A[35:3]# (I/O - GTL+) The A[35:3]# (Address) signals define a 236-byte physical memory address space. When ADS# is active, these signals transmit the address of a transaction; when ADS# is inactive, these signals transmit transaction information. These signals must be connected to the appropriate pins/balls of both agents on the system bus.
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® ® Mobile Intel Celeron Processor (0.18µ) in BGA2 and Micro-PGA2 Packages AP[1:0]# (I/O - GTL+) The AP[1:0]# (Address Parity) signals are driven by the request initiator along with ADS#, A[35:3]#, REQ[4:0]# and RP#. AP1# covers A[35:24]#. AP0# covers A[23:3]#. A correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low. This allows parity to be high when all the covered signals are high.
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® ® Mobile Intel Celeron Processor (0.18µ) in BGA2 and Micro-PGA2 Packages BNR# (I/O - GTL+) The BNR# (Block Next Request) signal is used to assert a bus stall by any bus agent that is unable to accept new bus transactions. During a bus stall, the current bus owner cannot issue any new transactions. Since multiple agents may need to request a bus stall simultaneously, BNR# is a wired-OR signal that must be connected to the appropriate pins/balls of both agents on the system bus.
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® ® Mobile Intel Celeron Processor (0.18µ) in BGA2 and Micro-PGA2 Packages Table 35. BSEL[1:0] Encoding BSEL[1:0] System Bus Frequency 00 66 MHz 01 100 MHz 10 Reserved 11 Reserved CLKREF (Analog) The CLKREF (System Bus Clock Reference) signal provides a reference voltage to define the trip point for the BCLK signal. This signal should be connected to a resistor divider to generate 1.25V from the 2.5V supply.
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® ® Mobile Intel Celeron Processor (0.18µ) in BGA2 and Micro-PGA2 Packages appropriate pins/balls on both agents on the system bus if they are used. During power-on configuration, DEP[7:0]# signals can be enabled for ECC checking or disabled for no checking. DRDY# (I/O - GTL+) The DRDY# (Data Ready) signal is asserted by the data driver on each data transfer, indicating valid data on the data bus. In a multi-cycle data transfer, DRDY# can be deasserted to insert idle clocks.
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® ® Mobile Intel Celeron Processor (0.18µ) in BGA2 and Micro-PGA2 Packages IGNNE# (I - 1.5V Tolerant) The IGNNE# (Ignore Numeric Error) signal is asserted to force the processor to ignore a numeric error and continue to execute non-control floating-point instructions. If IGNNE# is deasserted, the processor freezes on a non-control floating-point instruction if a previous instruction caused an error. IGNNE# has no affect when the NE bit in control register 0 (CR0) is set. INIT# (I - 1.
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® ® Mobile Intel Celeron Processor (0.18µ) in BGA2 and Micro-PGA2 Packages NC (No Connect) All signals named NC (No Connect) must be unconnected. NMI (I - 1.5V Tolerant) The NMI (Non-Maskable Interrupt) indicates that an external interrupt has been generated. NMI becomes the LINT1 signal when the APIC is disabled. Asserting NMI causes an interrupt with an internally supplied vector value of 2. An external interrupt-acknowledge transaction is not generated.
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® ® Mobile Intel Celeron Processor (0.18µ) in BGA2 and Micro-PGA2 Packages specifications. Clean implies that the signal will remain low, (capable of sinking leakage current) and without glitches, from the time that the power supplies are turned on, until they come within specification. The signal will then transition monotonically to a high (2.5V) state. Figure 24 illustrates the relationship of PWRGOOD to other system signals.
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® ® Mobile Intel Celeron Processor (0.18µ) in BGA2 and Micro-PGA2 Packages Unless its outputs are tri-stated during power-on configuration, after an active-to-inactive transition of RESET#, the processor optionally executes its built-in self-test (BIST) and begins program execution at reset-vector 000FFFF0H or FFFFFFF0H. RESET# must be connected to the appropriate pins/balls on both agents on the system bus.
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® ® Mobile Intel Celeron Processor (0.18µ) in BGA2 and Micro-PGA2 Packages leaving only the Phase-Locked Loop (PLL) still running. The processor will not recognize snoop and interrupts in the Sleep state. The processor will only recognize changes in the SLP#, STPCLK# and RESET# signals while in the Sleep state. If SLP# is deasserted, the processor exits Sleep state and returns to the Stop Grant state in which it restarts its internal clock to the bus and APIC processor units. SMI# (I - 1.
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® ® Mobile Intel Celeron Processor (0.18µ) in BGA2 and Micro-PGA2 Packages TESTLO[2:1] (I - 1.5V Tolerant) The TESTLO[2:1] (Test input Low) signals are used during processor test and needs to be pulled to ground during normal operation. THERMDA, THERMDC (Analog) The THERMDA (Thermal Diode Anode) and THERMDC (Thermal Diode Cathode) signals connect to the anode and cathode of the on-die thermal diode. TMS (I - 1.5V Tolerant) The TMS (Test Mode Select) signal is a JTAG support signal used by debug tools.
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® ® Mobile Intel Celeron Processor (0.18µ) in BGA2 and Micro-PGA2 Packages Table 36. Voltage Identification Encoding VID[4:0] VCC 00000 2.00 00001 1.95 00010 1.90 00011 1.85 00100 1.80 00101 1.75 00110 1.70 00111 1.65 01000 1.60 01001 1.55 01010 1.50 01011 1.45 01100 1.40 01101 1.35 01110 1.30 01111 No CPU 10000 1.275 10001 1.250 10010 1.225 10011 1.200 10100 1.175 10101 1.150 10110 1.125 10111 1.100 11000 1.075 11001 1.050 11010 1.025 11011 1.
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® ® Mobile Intel Celeron Processor (0.18µ) in BGA2 and Micro-PGA2 Packages 8.2 Signal Summaries Table 37 through Table 40 list the attributes of the processor input, output, and I/O signals. Table 37.
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® ® Mobile Intel Celeron Processor (0.18µ) in BGA2 and Micro-PGA2 Packages Table 38. Output Signals Name Active Level Clock Signal Group FERR# Low Asynch Open-drain IERR# Low Asynch Open-drain PRDY# Low BCLK Implementation TDO High TCK JTAG VID[4:0] High Asynch Implementation Table 39.
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® ® Mobile Intel Celeron Processor (0.18µ) in BGA2 and Micro-PGA2 Packages Appendix A: PLL RLC Filter Specification A.1 Introduction All mobile Intel Celeron processors have internal PLL clock generators, which are analog in nature and require quiet power supplies for minimum jitter. Jitter is detrimental to a system; it degrades external I/O timings as well as internal core timings (i.e. maximum frequency).
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® ® Mobile Intel Celeron Processor (0.18µ) in BGA2 and Micro-PGA2 Packages Figure 25. PLL Filter Specifications 0.2 dB 0 dB x dB forbidden zone -28 dB forbidden zone -34 dB DC 1 Hz fpeak 1 MHz 66 MHz fcore high frequency band passband x = 20.log[(Vcct-60 mV)/ Vcct] NOTES: 1. Diagram is not to scale 2. No specification for frequencies beyond fcore. 3. Fpeak, if existent, should be less than 0.05 MHz. A.3 Recommendation for Mobile Systems The following LC components are recommended.
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® ® Mobile Intel Celeron Processor (0.18µ) in BGA2 and Micro-PGA2 Packages Table 42. PLL Filter Capacitor Recommendations Capacitor Part Number Value Tolerance ESL ESR C1 Kemet T495D336M016AS 33 µF 20% 2.5 nH 0.225Ω C2 AVX TPSD336M020S0200 33 µF 20% unknown 0.2Ω NOTE: There may be other vendors who might provide parts of equivalent characteristics and the OEMs should consider doing their own testing for selecting their own vendors. Table 43.
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® ® Mobile Intel Celeron Processor (0.18µ) in BGA2 and Micro-PGA2 Packages The mobile Pentium II processor LC filter cannot be used with the mobile Intel Celeron processor. The larger inductor of the old LC filter imposes a lower current rating. Due to increased current requirements for the mobile Intel Celeron processor in the BGA2 and µPGA2 packages, a lower value inductor is required.