Vol 2

Intel
®
Xeon
®
Processor E7-2800/4800/8800 v2 Product Family 187
Datasheet Volume Two: Functional Description, February 2014
Processor Uncore Configuration Registers
13.7.4.6 CAPID4
This register is a Capability Register used to expose enable/disable for BIOS use.
13.7.4.7 RESOLVED_CORES_MASK
This RESOLVED_CORES_MASK register contains the Cores 0-7 enabled information in
the package.
§
Type: CFG PortID: N/A
Bus: 1 Device: 10 Function: 3
Offset: 0x94
Bit Attr Default Description
31:31 RO_FW 0x0 Disable DRAM Power Meter (DRAM_POWER_METER_DISABLE)
30:30 RO_FW 0x0 Disable DRAM RAPL (DRAM_RAPL_DISABLE)
29:29 RO_FW 0x0 Enable Intelligent Turbo (I_TURBO_ENABLE)
28:15 RV -
Reserved:
Reserved
14:0 RO_FW 0x0 LLC_SLICE_IA_CORE_EN
Type: CFG PortID: N/A
Bus: 1 Device: 10Function:3
Offset: 0xb0
Bit Attr Default Description
31:25 RV - Reserved.
24:24 RO_V 0x0
SMT Capability (SMT_CAPABILITY):
Enabled threads in the package.
0b - 1 thread
1b - 2 threads
23:16 RV - Reserved
9:8 RO_V 0x0
Thread Mask (THREAD_MASK):
Thread Mask indicates which threads are enabled in the core. The LSB is the
enable bit for Thread 0, whereas the MSB is the enable bit for Thread 1.
This field is determined by FW based on CSR_DESIRED_CORES[SMT_DISABLE].
7:0 RO_V 0x0
Core Mask (CORE_MASK):
The Core Mask indicates the enabled / active (non-defeatured) IA cores. The
mask is indexed by logical ID.
It is normally contiguous, unless BIOS defeature is activated on a particular
core. Processor will read this mask in order to decide on BSP and APIC IDs.
Note:
This field contains Core 0-7 information. The Core 8-14 can refer to
RESOLVED_CORES_MASK2[CORE_MASK].
This field is updated by the HW after reset based upon the value programed in
the CSR_DESIRED_CORES[CORE_OFF_MASK] field by the FW.