Specification Update

Errata
52 Intel
®
Xeon
®
Processor E7 v2 Product Family
Specification Update January 2015
CF136 Spurious Patrol Scrub Errors May Be Reported During Exit From Deep
Package C-States
Problem: When exiting from Package C3 or deeper, spurious Memory Scrubbing Errors may be
reported with IA32_MC(13-16)_STATUS.MCACOD with a value of
0000_0000_1100_CCCCb (where CCCC is the channel number).
Implication: The patrol scrub errors reported when this erratum occurs are uncorrectable and may
result in a system reset.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF137 Local PCIe* P2P Traffic on x4 Ports May Cause a System Hang
Problem: Under certain conditions, P2P (Peer-to-Peer) traffic between x4 PCIe ports on the same
processor (i.e., local) may cause a system hang.
Implication: Due to this erratum, the system may hang.
Workaround: None identified.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF138 NTB Operating In NTB/RP Mode May Complete Transactions With
Incorrect ReqID
Problem: When the NTB (Non-Transparent Bridge) is operating in NTB/RP (NTB Root Port mode)
it is possible for transactions to be completed with the incorrect ReqID (Requester ID).
This erratum occurs when an outbound transaction is aborted before a completion for
inbound transaction is returned.
Implication: Due to this erratum, a completion timeout and an unexpected completion may be seen
by the processor connected to the NTB/RP. Intel has not observed this erratum with
any commercially available system.
Workaround: None identified.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF139 Warm Reset May Cause PCIe And Memory Hot-Plug Sequencing
Failure
Problem: The Integrated I/O unit uses the VPP (Virtual Pin Port) to communicate with power
controllers, switches, and LEDs associated with PCIe/memory Hot-Plug sequencing.
Due to this erratum, a warm reset occurring when a VPP transaction is in progress may
result in an extended VPP stall, termination of the inflight VPP transaction, or a
transient power down of slots subject to VPP power control.
Implication: During or shortly after a warm reset, when this erratum occurs, PCIe/memory Hot-Plug
sequencing may experience transient or persistent failures or slots may experience
unexpected transient power down events. In certain instances, a cold reset may be
needed to fully restore operation.
Workaround: It is possible for the BIOS to contain a workaround for this erratum with respect to PCIe
Hot Plug.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF140 Performance Monitoring IA32_PERF_GLOBAL_STATUS.CondChgd Bit
Not Cleared by Reset
Problem: The IA32_PERF_GLOBAL_STATUS MSR (38EH) should be cleared by reset. Due to this
erratum, CondChgd (bit 63) of the IA32_PERF_GLOBAL_STATUS MSR may not be
cleared.
Implication: When this erratum occurs, performance monitoring software may behave
unexpectedly.