Hub Datasheet

Intel

E7505 Chipset MCH Datasheet 97

3.6.30 DRAM_UELOG_ADD—DRAM First Uncorrectable Memory

Error Address Register (D0:F1)

Address Offset: B0–B3h

Default Value: 0000 0000h

Sticky Yes

Attribute: RO

Size: 32 bits

This register contains the address of the first uncorrectable memory error. When a bit in either the

DRAM_FERR or DRAM_NERR Register is set, this register is locked. This register is only valid

if a bit in either the DRAM_FERR or DRAM_NERR Register is set.

3.6.31 DRAM_CELOG_SYNDROME—DRAM First Correctable

Memory Error Register (D0:F1)

Address Offset: D0–D1h

Default Value: 0000h

Sticky Yes

Attribute: RO

Size: 16 bits

This register contains the syndrome of the first correctable memory error. This register is locked

when a bit in either the DRAM_FERR or DRAM_NERR Register is set. If the bits in both registers

are set to 0, the DRAM_CELOG_SYNDROME can be updated; however, if a bit in either register

is set to 1, then DRAM_CELOG_SYNDROME will retain its value for logging purposes. This

Bits

Default,

Access

Description

31:28 Reserved

27:6

0000b

UE Address. This field contains address bits 33:12 of the first uncorrectable memory

error. The address bits are a physical address.

5:0 Reserved

Bits

Default,

Access

Description

15:0

0000h

ECC Syndrome for correctable error