Hub Datasheet

56 Intel
®
E7505 Chipset MCH Datasheet
Register Description
3.5.16 PAM[0:6]—Programmable Attribute Map Registers (D0:F0)
Address Offset: 59–5Fh (PAM0–PAM6)
Default Value: 00h
Access: R/W
Size: 8 bits each
The MCH allows programmable memory attributes on 13 legacy memory segments of various
sizes in the 768 KB to 1 MB address range. Seven Programmable Attribute Map (PAM) Registers
support these features. However, not all seven of these registers are identical. PAM 0 controls only
one segment (high), while PAM 1:6 controls two segments (high and low) each. Cacheability of
these areas is controlled via the MTRR Registers in the processor. Two bits are used to specify
memory attributes for each memory segment. These bits only apply to host initiator access to the
PAM areas. The MCH forwards to main memory any Hub Interface_A–B initiated accesses to the
PAM areas. At the time that hub interface accesses to the PAM region may occur, the targeted PAM
segment must be programmed to be both readable and writeable. It is illegal to issue a hub initiated
transaction to a PAM region with the associated PAM register not set to 11. Each of these regions
has a 2-bit field. The two bits that control each region have the same encoding.
As an example, consider BIOS that is implemented on the expansion bus. During the initialization
process, BIOS can be shadowed in main memory to increase the system performance. When BIOS
is shadowed in main memory, it should be copied to the same address location. To shadow the
BIOS, the attributes for that address range should be set to write only. The BIOS is shadowed by
first doing a read of that address. This read is forwarded to the expansion bus. The host then does a
write of the same address, which is directed to main memory. After the BIOS is shadowed, the
attributes for that memory area are set to read only so that all writes are forwarded to the expansion
bus. Table 3-3and Figure 3-1 show the PAM Registers and the associated attribute bits:
Bits
Default,
Access
Description
7:6 Reserved
5:4
00b
R/W
Attribute Register (HIENABLE). This field controls the steering of read and write cycles
that address the BIOS.
00 = DRAM Disabled - All accesses are directed to HI_A
01 = Read Only - All Reads are serviced by DRAM. All Writes are forwarded to HI_A.
10 = Write Only - All writes are sent to DRAM. Reads are serviced by HI_A.
11 = Normal DRAM operation - All reads and writes are serviced by DRAM
3:2 Reserved
1:0
00b
R/W
Attribute Register (LOENABLE). This field controls the steering of read and write cycles
that address the BIOS.
00 =DRAM Disabled - All accesses are directed to HI_A
01 =Read Only - All Reads are serviced by DRAM. All Writes are forwarded to HI_A.
10 =Write Only - All writes are sent to DRAM. Reads are serviced by HI_A.
1 1 =Normal DRAM operation - All reads and writes are serviced by DRAM
NOTE: The LO Segment for PAM0 is reserved as shown in Figure 3-1.