Hub Datasheet

Signal Description
28 Intel
®
E7505 Chipset MCH Datasheet
CKE_A[3:0]
O
SSTL-2
Clock Enable: CKE_x high activates, and CKE_x low deactivates the
internal clock signals, and device input buffers and output drivers. Driving
CKE_x low provides precharge powerdown and self refresh operation (all
banks idle), or Active Powerdown (row active in any bank). CKE_x is
synchronous for powerdown entry and exit, and for self refresh entry. CKE_x
is asynchronous for Self Refresh exit, and for output disable. Input buffers,
excluding CK, CK#, and CKE_x are disabled during powerdown. Input
buffers, excluding CKEx are disabled during self refresh.
The CKE signals are driven low when the RSTIN# signal is low to keep the
DRAMs in self refresh mode.
Registered: One for even rows, one for odd rows. Unbuffered: One per row.
RCVENOUT_A#
O
SSTL-2
Receive Enable Output: This signal is driven low and fed back internally
when the DQ bus is to receive data (DRAM reads). It is used to set the
timing for enabling the DQS input buffers so that they are enabled only when
driven by the DRAMs. This signal must be terminated externally.
DVREF_A
I
Analog
Voltage Reference
DRCOMP_H
I/O
SSTL-2
Compensation for DDR Horizontal Direction: This signal is used to
calibrate the DDR buffers. Used for both channels on the horizontal direction
buffers. Externally it is connected to a 25 Ω resistor to ground.
DRCOMPVREF_H Analog
RComp VREF: This signal is used for both channels on the horizontal
direction buffers. This pin is connected to an external voltage derived from a
resistor network.
ODTCOMP
I/O
SSTL-2
On-Die termination RCOMP: This signal provides compensation for the
On-Die Termination for the DDR interface. It is connected to an external
402 Ω 1% resistor for on die termination.
Table 2-2. DDR Channel A Signals (Sheet 3 of 3)
Signal Name Type Description
Signal 2 DIMM MB 3 DIMM MB
CKE_A3 DIMM 1 CKE1
CKE_A2 DIMM 1 CKE0
CKE_A1 DIMM 0 CKE1 All DIMMs CKE1
CKE_A0 DIMM 0 CKE0 All DIMMs CKE0