Hub Datasheet

Signal Description
24 Intel
®
E7505 Chipset MCH Datasheet
DRDY#
I/O
AGTL+
Data Ready: This signal is asserted for each cycle that data is transferred.
HA[35:3]#
I/O
GTL+
2x
Host Address Bus: HA[35:3]# connect to the system address bus. During
processor cycles, HA[35:3]# are inputs. The MCH drives HA[35:3]# during
snoop cycles on behalf of HI initiators. HA[35:3] are transferred at 2x rate.
HADSTB[1:0]#
I/O
AGTL+
2x
Host Address Strobe: The source synchronous strobes are used to transfer
HA[35:3]# and HREQ[4:0]# at the 2x transfer rate.
HD[63:0]#
I/O
AGTL+
4x
Host Data: These signals are connected to the system data bus. HD[63:0]# are
transferred at the 4x rate.
HDSTBP[3:0]#,
HDSTBN[3:0]#
I/O
AGTL+
4x
Differential Host Data Strobes: The differential source synchronous strobes
are used to transfer HD[63:0]# and DINV[3:0]# at the 4x transfer rate.
Strobe Data Bits
HDSTBP3#, HDSTBN3# HD[63:48]#, DINV3#
HDSTBP2#, HDSTBN2# HD[47:32]#, DINV2#
HDSTBP1#, HDSTBN1# HD[31:16]#, DINV1#
HDSTBP0#, HDSTBN0# HD[15:0]#, DINV0#
HIT#
I/O
AGTL+
Hit: This signal indicates that a caching agent holds an unmodified version of
the requested line. Also, driven in conjunction with HITM# by the target to
extend the snoop window.
HITM#
I/O
AGTL+
Hit Modified: This signal indicates that a caching agent holds a modified
version of the requested line and that this agent assumes responsibility for
providing the line. HITM# is driven in conjunction with HIT# to extend the snoop
window.
HLOCK#
I
AGTL+
Host Lock: All system bus cycles are sampled with the assertion of HLOCK#
and ADS#, until the negation of HLOCK#. Must be atomic, i.e., no Hub Interface
or AGP snoopable access to DRAM are allowed when HLOCK# is asserted by
the processor.
HREQ[4:0]#
I/O
AGTL+
2x
Host Request Command: These signals define the attributes of the request. In
Enhanced Mode HREQ[4:0]# are transferred at the 2x rate. The request is
asserted by the requesting agent during both halves of a Request Phase. In the
first half the signals define the transaction type to a level of detail that is
sufficient to begin a snoop request. In the second half the signals carry
additional information to define the complete transaction type.
HTRDY#
O
AGTL+
Host Target Ready: This signal indicates that the target of the processor
transaction is able to enter the data transfer phase.
RS[2:0]#
O
AGTL+
Response Signals: The RS[2:0]# signals indicate the type of response
according to the following:
000 = Idle state
001 = Retry response
010 = Deferred response
011 = Reserved (not driven by MCH)
100 = Hard Failure (not driven by MCH)
101 = No data response
110 = Implicit Writeback
111 = Normal data response
RSP#
O
AGTL+
Response Parity: RSP# provides parity protection for the RS[2:0]# signals.
RSP# is always driven by the MCH and must be valid on all clocks. Response
parity is correct when there are an even number of low signals (low voltage) in
the set consisting of the RS[2:0]# signals and the RSP# signal itself.
Table 2-1. Host Interface Signals (Sheet 2 of 3)
Signal Name Type Description