Hub Datasheet

Intel
®
E7505 Chipset MCH Datasheet 215
Testability
Testability 8
For Automated Test Equipment (ATE), the MCH supports XOR-tree testing. XOR-tree testing
allows board-level interconnections to be tested. An XOR-Tree is a chain of XOR gates, with each
having one input pin or one bi-directional pin (used as an input pin only) connected to it.
8.1 XOR Test Mode Initialization
XOR mode can be entered by driving the XORMODE# pin (ball G1) low. Clocks may be inactive
during this test mode. This mode is intended to be asynchronous.
• Drive RSTIN#, XORMODE#, PWRGD High.
• Drive RSTIN# (reset) pin Low and then High again. (This resets the part)
• Then drive the XORMODE# pin Low. (This puts the part into XOR mode)
• Drive all the PADs in a chain to 1, and observe the chain output at the assigned HI_A[x]
(visibility) pin.
• Drive one of the PADs in the same chain to 0, and observe the chain output toggle.
• Similarly test all XOR chains while cycling through all PAD inputs.
8.1.1 XOR Chains
The following pages contain the XOR Chain information.
Note: To keep the XOR Chain contiguous, the RESERVED signals must have an accessible test point if
XOR Testing is to be implemented.
Figure 8-1. XOR Test Tree Chain
Input
XOR
Out
or sd
Input Input Input Input
VCC1_2