Hub Datasheet

166 Intel
®
E7505 Chipset MCH Datasheet
Functional Description
5.5.1 Frequency and Bandwidth
In the MCH, the same core clock frequency is used for the processor system bus and the memory
interface. The system bus and memory interface frequencies must be operating synchronously
(see Table 5-7).
NOTE: A 266 MT/s DRAM can be used with a processor supporting a 400 MHz system bus, although the
memory interface will be operating at 100 MHz and not 133 MHz.
5.5.2 Memory Operation
The MCH contains a dual-channel DDR interface, with each channel having 64 data bits and 8
ECC bits. The memory interface channels operate in “lock-step” with each other. The data is a
double QWord interleaved between the channels with the low DQWord on channel A and the high
DQWord on channel B. A burst of four data items, that takes two clocks, is required for one cache
line (64 bytes). A 256-bit interface transfers the data at the core clock frequency internally,
matching the memory bandwidth.
The memory must be populated in identical DIMM configurations (i.e., Slot 0 of channel A must
contain the same configuration DIMM as Slot 0 of channel B). The configuration consists of the
same number of rows (1 or 2), the same technology part (128 Mb, 256 Mb, 512 Mb, or 1 Gb), the
same DRAM chip width (x4, x8, or 16), and the same speed.
Note: When the MCH is configured as a Registered DIMM platform only, the user must populate the
memory modules in the following manner:
• Channel A and Channel B must contain the same memory configuration as described above.
• First populate the furthest DIMM slot (within the channel) respective to the MCH.
Page
A page is a section of a DRAM bank that is opened by an activate command. Once
opened, multiple locations (columns) of a page can be read or written without requiring
a precharge and activate command.
Row Address
The row address is presented to the DRAMs during an Activate command and
indicates which page to open within the specified bank (the bank number is also
presented).
Column Address
The column address selects one DRAM location (or the starting location of a burst)
from within the open page on a read or write command.
Channel
In the MCH, a DRAM Channel is the set of signals that connect to one set of DRAM
DIMMs. The MCH has two DRAM channels, (a pair of DIMMs added at a time, one on
each channel).
Table 5-6. DRAM Terminology (Continued)
Term Definition
Table 5-7. Supported System Bus and Memory Interface Configurations
System Bus
Clock
System Bus
Transfer/s
System Bus BW
DRAM
Clock
DRAM
Transfer/s
DDR BW
133 MHz 533 MT/s 4.27 GB/s 133 MHz 266 MT/s 4.27 GB/s
100 MHz 400 MT/s 3.2 GB/s 100 MHz 200 MT/s 3.2 GB/s