Hub Datasheet

156 Intel
®
E7505 Chipset MCH Datasheet
Functional Description
5.1.4 Dynamic Bus Inversion
The MCH supports Dynamic Bus Inversion (DBI) when driving and when receiving data from the
processor. DBI limits the number of data signals that are driven to a low voltage on each quad
pumped data phase. This decreases the worst-case power consumption of the MCH. The
DINV[3:0]# signals indicate if the corresponding 16 bits of data are inverted on the bus for each
quad pumped data phase (see following table).
When the processor or the MCH drives data, each 16-bit segment is analyzed. If more than 8 of the
16 signals would normally be driven low on the bus, the corresponding DINV# signal will be
asserted and the data will be inverted prior to being driven on the bus. When the processor or the
MCH receives data, it monitors DINV[3:0]# to determine if the corresponding data segment should
be inverted.
Dynamic Bus Inversion (DBI) is a technique used to guarantee that a maximum of half the data
signal values are active (1 internally or 0 on the System Bus). This mechanism groups the data bus
into groups of 16 signals. In every group the number of active signals is counted, if more than eight
active signals are present, the group’s signals are inverted and the inversion indication (DINV
internally, DINV# on the System Bus) is activated; otherwise, the group is not inverted.
DBI is used to minimize signal switching within a group of 16 data signals and minimize on-die
terminations’ power consumption. DBI specification requires that, for most of the time, there will
be no more than 8 active data signals in a group of 16. It requires that there will never be more than
9 active data signals in a group of 16.
5.1.5 System Bus Interrupt
Interrupt-related messages are encoded on the system bus as “Interrupt Message Transactions.” In
the MCH platform system bus interrupts may originate from the processor on the system bus
(IPIs- inter-processor interrupts), from a downstream device on the hub interface, or AGP. In the
later case the MCH drives the “Interrupt Message Transaction” onto the system bus.
The ICH4 contains an IOxAPIC. Interrupts are generated to a processor in the form of upstream
hub interface memory writes. The PCI Local Bus Specification, Revision 2.2 defines MSIs
(Message Signaled Interrupts) that are also in the form of memory writes. A PCI 2.2 device may
generate an interrupt as an MSI cycle on its PCI bus instead of asserting a hardware signal to the
IOxAPIC. The MSI may be directed to the IOxAPIC which in turn generates an interrupt as an
upstream hub interface memory write. Alternatively, the MSI may be directed directly to the
system bus. The target of an MSI is dependent on the address of the interrupt memory write. The
MCH forwards inbound hub interface memory writes to address 0FEEx_xxxxh to the system bus
as “Interrupt Message Transactions.”
DINV[3:0]# Data Bits
DINV0# HD[15:0]#
DINV1# HD[31:16]#
DINV2# HD[47:32]#
DINV3# HD[63:48]#