Hub Datasheet

130 Intel
®
E7505 Chipset MCH Datasheet
Register Description
3.8.15 SEC_STS2—Secondary Status Register (D2:F0)
Address Offset: 1E–1Fh
Default Value: 02A0h
Attribute: R/WC, RO
Size: 16 bits
SSTS2 is a 16-bit status register that reports the occurrence of error conditions associated with
secondary side (i.e., HI_B side) of the virtual PCI-to-PCI bridge in the MCH.
Note: Software writes a 1 to clear bits that are set.
Bits
Default,
Access
Description
15
0b
R/WC
Detected Parity Error (2DPE).
0 = No error for reported condition
1 = MCH detected a parity error in the address or data phase of HI_B bus transactions.
14
0b
R/WC
Received System Error (2RSE).
0 = No error for reported condition
1 = MCH receives an SERR message on HI_B.
13
0b
R/WC
Received Master Abort Status (2RMAS).
0 = No received Master Abort completion packet on HI_B.
1 = MCH received a Master Abort completion packet on HI_B.
12
0b
R/WC
Received Target Abort Status (2RTAS).
0 = No received Target Abort completion packet on HI_B.
1 = MCH received a Target Abort completion packet on HI_B.
11
0b
RO
Signaled Target Abort Status (STAS). Hardwired to 0. MCH does not generate target
aborts on HI_B.
10:9
01b
RO
DEVSEL# Timing (DEVT). Hardwired to 01. This concept is not supported on HI_B.
8
0b
RO
Master Data Parity Error Detected (DPD). Hardwired to 0. The MCH does not
implement PERR messaging on HI_B.
7
1b
RO
Fast Back-to-Back (FB2B). Hardwired to 0. This concept is not supported on HI_B.
6 Reserved
5
1b
RO
66/60 MHz capability (CAP66). Hardwired to 1. This indicates that HI_B is enabled for
66 MHz operation.
4:0 Reserved