Specification Update

Intel
®
E7320 Memory Controller Hub (MCH) Specification Update 11
Errata
5. Incorrect PCI Express Link/Lane numbers driven in degraded link
Problem: If a failure of receiver detect or bit/symbol lock occurs on lane 0 (lane 7 in the case of physical lane
reversal) while other lanes successfully achieve bit/symbol lock in the early stages of
Polling.Active, the MCH will exhibit anomalous lane numbering during the ensuing failed training
sequence. Note that this anomalous behavior only occurs in situations where the combination of
successful and failing lanes will result in a training failure, and a return to the Polling state.
Implication: When such a failed training is in progress, non-compliant non-PAD lane numbers may be observed
on the MCH downstream lanes. The observed behavior may be seen as the MCH attempting a link
split.
Workaround: None
Status: For the steppings effected, see the Summary Table of Changes.
6. PCI Express Compliance Mode issue
Problem: When a x8 link exits PCI Express Compliance Mode, the MCH will attempt to retrain as two x4
links. This issue manifests itself when the MCH inadvertently enters Compliance Mode.
Implication: Upon exiting Compliance Mode, the MCH link will attempt to train a downstream x8 device as two
separate x4 links. Depending on the capabilities of the downstream device, the link width will be
configured as either x4 or x1.
Workaround: Set bit 0 to 1b in Bus 0, Device 0, Function 0, Offset F5h. This will force the MCH to not enter
compliance mode. Note that the MCH defaults to Compliance Mode disabled.
Status: For the steppings effected, see the Summary Table of Changes.
7. PCI Express link training failures on hot reset
Problem: When issuing a hot reset via the bridge control register (BCTRL, Bus 0, Device 2-3, Function 0,
Offset 3Eh bit 6, 1b) secondary bus reset bit to a PCI Express slot, the link may fall back degraded
to a lower link width.
Implication: The link may degrade in width or fail to train all together after a hot reset.
Workaround: Implement a software algorithm that issues a Secondary Bus Reset upon a link training failure for
2 ms. The algorithm should support at least three iterations of Secondary Bus Resets.
Status: For the steppings effected, see the Summary Table of Changes.
8. Subsystem Identification and Subsystem Vendor Identification register
issue
Problem: The Subsystem Vendor Identification register (SVID, Bus 0, D0:F0/F1, D1:F0, D2:F0 & D8:F0,
Offset 2C-2Dh) and the Subsystem Identification register (SID, Bus 0, D0:F0/F1, D1:F0, D2:F0 &
D8:F0, Offset 2E-2Fh) are not able to be written to independently. Writing to one register causes
both to become Read Only.
Implication: If the values written to these two registers are not written via the Dword address, then the second
value written will not be set.
Workaround: Write to both registers at the same time using PCI configuration Dword writes.
Status: For the steppings effected, see the Summary Table of Changes.
9. MCH responds with illegal access on the Hub Interface for 32 GB
configurations
Problem: When devices behind the ICH try to access a memory address above 4 GB in systems with 32 GB
of physical memory, an illegal access error is incorrectly flagged by the MCH.