Datasheet

Features
Dual-Core Intel
®
Xeon
®
Processor 7000 Series Datasheet 91
7.4.9.3.2 Front Side Bus Frequency
Offset 1A - 1Bh provides FSB frequency information. Systems may need to read this offset to
decide if all installed processors support the same FSB speed. Because the Intel NetBurst
®
microarchitecture bus is described as a 4x data bus, the frequency given in this field is currently
667 MHz. The data provided is the speed, rounded to a whole number, and reflected in hex.
Example: The Dual-Core Intel Xeon processor 7000 series supports a 667 MHz FSB. Therefore,
offset 1A - 1Bh has a value of 029Bh.
7.4.9.3.3 Multi-Processor Support
Offset 1Ch has 2 bits defined for representing the supported number of physical processors on the
bus. These two bits are MSB aligned where 00b equates to single-processor operation, 01b is a
dual-processor operation, and 11b represents multi-processor operation. Normally, only values of
01 and 11b are used. The remaining six bits in this field are reserved for the future use.
7.4.9.3.4 Maximum Core Frequency
Offset 1D - 1Eh provides the maximum core frequency for the processor. The frequency should
equate to the markings on the processor and/or the QDF/S-spec speed even if the parts are not
limited or locked to the intended speed. Format of this field is in MHz, rounded to a whole number,
and encoded in hex format.
Example: A 2.8 GHz processor will have a value of 0AF0h, which equates to 2800 decimal.
7.4.9.3.5 Core Voltage
There are two areas defined in the PIROM for the core voltages associated with the processor.
Offset 1F - 20h is the Processor Core VID (Voltage Identification) field and contains the voltage
requested via the VID pins. In the case of the Dual-Core Intel Xeon processor 7000 series, this is
1.3875 V. This field, rounded to the next thousandth, is in mV and is reflected in hex. This data is
also in Table 2-8. Some systems read this offset to determine if all processors support the same
default VID setting.
Minimum core voltage is reflected in offset 21 – 22h. This field is in mV and reflected in hex. The
minimum VCC reflected in this field is the minimum allowable voltage assuming the FMB
maximum current draw.
Note: The minimum core voltage value in offset 21 – 22h is a single value that assumes the FMB
maximum current draw. Refer to Table 2-8. for the actual minimum core voltage specifications
based on actual real-time current draw.
Example: The specifications for a Dual-Core Intel Xeon processor 7000 series at FMB are 1.4125
V VID and 1.200 V minimum voltage. Offset 1F - 20h would contain 585h (1413 decimal) and
offset 21 - 22h would contain 4B0h (1200 decimal).
7.4.9.3.6 T
CASE
Maximum
The last field within Processor Core Data is the T
CASE
Maximum field. The field reflects
temperature in degrees Celsius in hex format. This data can be found in the Table 6-1. In the case of
the Dual-Core Intel Xeon processor 7000 series, the thermal specifications are specified at the case
(IHS).