Vol 1

Intel® Xeon® Product 2800/4800/8800 v2 Product Family 71
Datasheet Volume One, February 2014
Electrical Specifications
Clock multiplying within the processor is provided by the internal phase locked loop
(PLL), which requires a constant frequency BCLK{0/1}_DP, BCLK{0/1}_DN input, with
exceptions for spread spectrum clocking. DC specifications for the BCLK{0/1}_DP,
BCLK{0/1}_DN inputs are provided in Table 6-21 and AC specifications in Table 6-26.
These specifications must be met while also meeting the associated signal quality
specifications outlined in Section 6.12.
Details regarding BCLK{0/1}_DP, BCLK{0/1}_DN driver specifications are provided in
the CK420BQ Clock Synthesizer/Driver Specification.
6.1.6.1 PLL Power Supply
An on-die PLL filter solution is implemented on the processor.
6.1.7 JTAG and Test Access Port (TAP) Signals
Due to the voltage levels supported by other components in the JTAG and Test Access
Port (TAP) logic, Intel recommends the processor be first in the TAP chain, followed by
any other components within the system. A translation buffer should be used to
connect to the rest of the chain unless one of the other components is capable of
accepting an input of the appropriate voltage. Two copies of each signal may be
required with each driving a different voltage level.
6.1.8 Processor Sideband Signals
Intel® Xeon® E7 v2 processors include asynchronous sideband signals that provide
asynchronous input, output or I/O signals between the processor and the platform or
Platform Controller Hub. Details can be found in Table 6-5.
All Processor Asynchronous Sideband input signals are required to be
asserted/deasserted for a defined number of BCLKs in order for the processor to
recognize the proper signal state, these are outlined in Table 6-21 and Table 6-28
(DC and AC specifications). Refer to Section 6.12 for applicable signal
integrity specifications.
6.1.9 Power, Ground and Sense Signals
Processors also include various other signals including power/ground and sense points.
Details can be found in Table 6-5.
6.1.9.1 Power and Ground Lands
All V
CC
, V
CCPLL,
V
SA
, V
CC33,
V
TT
, and V
VMSE
lands must be connected to their
respective processor power planes, while all V
SS
lands must be connected to the
system ground plane.
For clean on-chip power distribution, processors include lands for all required voltage
supplies. These are listed in Table 6-1.