Vol 1

Intel® Xeon® Product 2800/4800/8800 v2 Product Family 69
Datasheet Volume One, February 2014
Electrical Specifications
6 Electrical Specifications
6.1 Processor Signaling
Intel® Xeon® E7 v2 processors include 2011 lands, which utilize various signaling
technologies. Signals are grouped by electrical characteristics and buffer type into
various signal groups. These include Intel® Scalable Memory Interface Gen 2 (Intel
SMI2) (Reference Clock, Command, Control, and Data), PCI Express*, DMI2, Intel®
QuickPath Interconnect, Platform Environmental Control Interface (PECI), System
Reference Clock, SMBus, JTAG and Test Access Port (TAP), SVID Interface, Processor
Asynchronous Sideband, Miscellaneous, and Power/Other signals. Refer to Table 6-5
for details.
Intel strongly recommends performing analog simulations of all interfaces. Please refer
to Section 1.7, “Related Documents” for signal integrity model availability.
6.1.1 System Memory Interface Signal Groups
The system memory interface utilizes Intel SMI2 technology, which consists of
numerous signal groups. These include: Reference Clocks, Command Signals, Control
Signals, and Data Signals. Each group consists of numerous signals, which may utilize
various signaling technologies. Please refer to Table 6-5 for further details. Throughout
this chapter the system memory interface maybe referred to as Intel SMI2.
6.1.2 PCI Express Signals
The PCI Express Signal Group consists of PCI Express* ports 1 and 2 and PCI Express
miscellaneous signals. Please refer to Table 6-5 for further details.
6.1.3 DMI2/PCI Express Signals
The Direct Media Interface Gen 2 (DMI2) sends and receives packets and/or commands
to the PCH. The DMI2 is an extension of the standard PCI Express Specification. The
DMI2/PCI Express Signals consist of DMI2 receive and transmit input/output signals
and a control signal to select DMI2 or PCIe* 2.0 operation for port 0. Please refer to
Table 6-5 for further details.
6.1.4 Intel® QuickPath Interconnect (Intel® QPI)
The Intel® Xeon® E7 v2 processor provides two Intel QPI ports for high-speed serial
transfer between other processors. Each port consists of two uni-directional links (for
transmit and receive). A differential signaling scheme is utilized, which consists of
opposite-polarity (DP, DN) signal pairs.