Update

Intel
®
Xeon
®
Processor E7-8800/4800/2800 Product Families 9
Specification Update November 2014
Table 1. Errata Table (Sheet 1 of 2)
Number
Stepping
Status Description
A-2
BP1. XNo Fix
Intel
®
Interconnect BIST (Intel
®
IBIST) Does Not Work in Intel
®
QuickPath Interconnect
(Intel
®
QPI) in Slow Mode
BP2. XNo FixRetraining Parameter Negotiation is Not Implemented for Intel
®
QPI
BP3. XNo FixIntel
®
IBIST Slave Ignores Loop Count Values Sent by Master on Intel
®
QPI
BP4. XNo FixSystem Hangs when Skipping Stop Req2 and Start Req1 Messages in Quiesce/Lock Sequence
BP5. XNo Fix
Integrated Memory Controller Signals Spurious CMCI when Home Agent Failover Count
Saturation Occurs
BP6. XNo Fix
Memory Controller Does Not Set S Bit for Uncorrectable Error Followed by Software
Recoverable Error
BP7. XNo FixMCi_STATUS S Bit Not Set for LLC Software Recoverable Errors
BP8. XNo FixCorrectable SB CRC Error May be Propagated to an Uncorrected ECC Error
BP9. XNo Fix
Memory Controller Patrol Scrub Ceases to Function with CRC Errors and the IMT31 Reclaim
Feature Enabled
BP10. XNo Fix
Electrically Idle Intel
®
SMI and Intel
®
QPI Lanes May Deliver Data that May Look Like Deskew
Headers
BP11. XNo Fix
A Sequence of Instruction Fetches and Snoops to Locked Cache Lines May Cause Processor to
Hang
BP12. XNo Fix
Writing to Unimplemented Bits of UU_CR_U_MSR_PMON_EVNT_SEL MSR does Not Result in
#GP Fault
BP13. XNo FixMixed Rank Size Memory Configurations May Cause a Missing Refresh Event
BP14. XNo Fix
Mirror Slave May Deliver Incorrect Data when a Read to the Mirror Master Completes Before the
Write-back from the IOH
BP15. XNo FixUU_CR_U_MSR_PMON_GLOL_OVF_CTL MSR Does Not Follow RW1C Access Method
BP16. XNo FixHNID Field is Incorrect for CMP Messages From PrefetchHint
BP17. XNo FixPage Fault May Occur When Logical Processor Transitions From C6 State to C0 State
BP18. XNo FixIn DAS Enabled Mode a System Hang May Occur During Memory Intensive Workloads
BP19. XNo FixBit [8] of IA32_APIC_BASE register Inadvertently Set to 1 for Core 9
BP20. XNo Fix
Quad Rank DIMMs With CKE Low Enabled in Open/Adaptive Page Mode May Return Incorrect
Data
BP21. XNo FixSystem Configuration Controller Misaligned Error May Result in a System Hang
BP22. XNo Fix
Recoverable Errors Signaled From Intel
®
QPI or Intel
®
SMI Port to the System Configuration
Controller May Get Lost if the Ports are Disabled
BP23. XNo Fix
Executing The WAKEUP Leaf of The GETSEC Instruction Multiple Times May Lead to a Machine
Check Error
BP24. XNo FixCKE-Lo Feature Can Not be Disabled When Memory Controller Transactions are Active
BP25. XNo FixExecuting The Intel TXT GETSEC SENTER Instruction Leaf May Lead to a Machine Check Error
BP26. XNo FixTask Switch to a TSS With an Inaccessible LDTR Descriptor May Cause Unexpected Faults
BP27. XNo Fix
An Intel
®
QPI Link Layer Retry Quickly Followed by an Intel
®
QPI Physical Layer Reset May
Cause an MCE
BP28. XNo FixLLC Arrays May have Incorrect Values after Warm Reset when Memory BIST is Disabled
BP29. XNo FixVM Entries that Return from SMM May Incorrectly Write to the SMRR Protected Region
BP30. XNo FixSystem Quiesce Events Initiated While Power Events are In Progress May Cause System Hangs
BP31. XNo Fix
Uncorrected Memory Error Detected by a Memory Patrol Scrub With SMI Generated by Other
Memory Controllers May Cause MCE/System Management Interrupt Race Condition
BP32. XNo Fix
Broken trace to either the P or the N lane of the Intel
®
SMI forwarded clock differential pair
may result in loss of forwarded clock but not always lead to clock lane failover.