Hub Datasheet
64 Intel
®
E7505 Chipset MCH Datasheet
Register Description
3.5.20 DRC—DRAM Controller Mode Register (D0:F0)
Address Offset: 7C–7Fh
Default Value: 0044_0009h
Attribute: RO, R/W
Size: 32 bits
Bits
Default,
Access
Description
31:30
00
b
RO
Revision Number (REV). This field reflects the revision number of the format used for
SDR/DDR register definition.
29
0b
R/W
Initialization Complete (IC). This bit is used for communication of software state
between the memory controller and the BIOS. BIOS sets this bit to 1 after initialization
of the DRAM memory array is complete. Note the following:
• Periodic refresh will not start until this bit is set.
• tRC timing counter is not enabled until this bit is set.
28:22 Reserved
21:20 00b
DRAM Data Integrity Mode (DDIM). These bits select one of 4 DRAM data integrity
modes.
DDIM Operation
00 Non-ECC mode, no ECC correction is done and no errors are flagged in
FERR or NERR
01 Reserved
10 Error checking, with correction
11 Reserved
19:18 Reserved
17
0b
R/W
Fast CS# Enable (FCSEN). This bit enables/disables Fast CS# mode.
0 = Disable.
1 = Enable. When set to 1, and when the DRAM interface is idle, CS# is asserted in
the same time the DRAM tracking transitions to active state. This mode of
operation reduces leadoff access latency by one clock and is used in selected
configurations (with light loads on address and command lines).
16
0b
R/W
Command Per Clock- Address/Control Assertion Rule (CPC). This bit defines the
number of clock cycles the MA, RAS#, CAS#, WE# are asserted.
0 = 2n rule: (MAx:x, RAS#, CAS#,WE# asserted for 2 clock cycles
1 = 1n rule: (MAx:x, RAS#, CAS#,WE# asserted for 1 clock cycles
13
0b
R/W
Auto-Precharge for Read Enable (APR).
0 = Disable. All reads are sent without auto-precharge
1 = Enable. All reads are sent with Auto-precharge attribute attached.
12
0b
R/W
Auto-Precharge for Write Enable (APW).
0 = Disable. All writes commands are sent without auto-precharge.
1 = Enable. All write commands are sent with auto-precharge attribute attached.
11 Reserved
10:8
000b
R/W
Refresh Mode Select (RMS). This field determines whether refresh is enabled and, if
so, at what rate refreshes will be executed.
000 = Disable
001 = Enable. Refresh interval 15.6 µs
010 = Enable. Refresh interval 7.8 µs
011 = Enable. Refresh interval 64 µs
111 = Enable. Refresh interval 64 clocks (fast refresh mode)
Others = Reserved
7 Reserved