Hub Datasheet

Intel
®
E7505 Chipset MCH Datasheet 51
Register Description
3.5.10 APBASE—Aperture Base Configuration Register (D0:F0)
Address Offset: 10–13h
Default Value: 0000 0008h
Attribute: RO, RW
Size: 32 bits
The APBASE is a standard PCI Base Address register that is used to set the base of the Graphics
Aperture. The standard PCI Configuration mechanism defines the base address configuration
register such that only a fixed amount of space can be requested (dependent on which bits are
hardwired to 0 or behave as hardwired to 0). To allow for flexibility (of the aperture) an additional
register called APSIZE is used as a “back-end” register to control which bits of the APBASE will
behave as hardwired to 0. This register will be programmed by the MCH specific BIOS code that
will run before any of the generic configuration software is run. Set by BIOS.
Note: The intention is that the APSIZE register force individual bits to Read Only as 0; however, the
MCH (and other chips) implementation only causes them to be read only, and does not force them
to 0. The default is 0, so the difference only occurs if the aperture is set to a small size, specific
APBASE bits are set to 1s, and the aperture size is then increased. APBASE bits affected by the
APSIZE change are then RO as whatever value had previously been written. While this could
cause bits to read back as 1 instead of 0, the actual aperture decode will be done properly according
to the APSIZE register. Software can avoid this situation by writing the APBASE register to 0 prior
to increasing the aperture size via APSIZE. The aperture should be disabled prior to any change in
APBASE or APSIZE.
Note: Bit 9 of the MCHCFG register is used to prevent accesses to the aperture range before this register
is initialized by the configuration software and the appropriate translation table structure has been
established in the main memory.
Bits
Default,
Access
Description
31:28
0h
R/W
Upper Programmable Base Address (UPBITS). These bits are part of the aperture
base set by configuration software to locate the base address of the graphics
aperture. They correspond to bits 31:28 of the base address in the processor’s
address space that will cause a graphics aperture translation to be inserted into the
path of any memory read or write.
27:22
00h
RW or RO
depending
on aperture
size
Middle Hardwired/Programmable Base Address (MIDBITS). These bits are part of
the aperture base set by configuration software to locate the base address of the
graphics aperture. They correspond to bits 27:4 of the base address in the
processor’s address space that will cause a graphics aperture translation to be
inserted into the path of any memory read or write. These bits can individually behave
as read only if programmed to do so by the APSIZE bits of the APSIZE register. This
causes configuration software to understand that the granularity of the graphics
aperture base address is either finer or more coarse, depending upon the bits set by
MCH-specific configuration software in APSIZE.
21:4
00000h
RO
Lower Bits (LOWBITS). Hardwired to 00000h. This forces the minimum aperture
size selectable by this register to be 4 MB without regard to the aperture size
definition enforced by the APSIZE register.
3
1b
RO
Prefetchable (PF). Hardwired to 1. This identifies the Graphics Aperture range as
perfectible, as per the PCI specification for base address registers. Thus, there are no
side effects on reads, the device returns all bytes on reads regardless of the byte
enables, and the MCH can merge processor writes into this range without causing
errors.
2:1
00b
RO
Addressing Type (TYPE). Hardwired to 00. This indicates that address range
defined by the upper bits of this register can be located anywhere in the 32-bit
address space as per the PCI specification for base address registers.
0
0b
RO
Memory Space Indicator (MSPACE). Hardwired to 0. This identifies the aperture
range as a memory range as per the specification for PCI base address registers.