Hub Datasheet

Intel

E7505 Chipset MCH Datasheet 41

A disabled or non-existent device’s configuration register space is hidden, returning all 1s for reads

and dropping writes just as if the cycle terminated with a Master Abort on PCI.

The MCH automatically detects if devices are connected to HI_B by sampling the corresponding

REQI signal on the rising edge of RSTIN#. When a hub interface is unpopulated, the associated

configuration register space is hidden, returning all 1s for all registers just as if the cycle terminated

with a Master Abort on PCI.

Logically, the ICH4 appears as multiple PCI devices within a single physical component also

residing on PCI bus #0. One of the ICH4 devices is a PCI-to-PCI bridge. Logically, the primary

side of the bridge resides on PCI #0 while the secondary side is the standard PCI expansion bus.

Note: A physical PCI bus #0 does not exist. HI_A and the internal devices in the MCH and ICH4

logically constitute PCI Bus #0 to configuration software.

3.2.1 PCI Bus Configuration Mechanism

The PCI Bus defines a slot-based configuration space that allows each device to contain up to eight

functions; each function contains up to 256, 8-bit configuration registers. The PCI specification

defines two bus cycles to access the PCI configuration space: Configuration Read and

Configuration Write. Memory and I/O spaces are supported directly by the processor.

Configuration space is supported by a mapping mechanism implemented within the MCH. The PCI

specification defines two mechanisms to access configuration space, Mechanism 1 and

Mechanism 2. The MCH supports only Mechanism 1.

The configuration access mechanism makes use of the CONFIG_ADDRESS register and

CONFIG_DATA register. To reference a configuration register a Dword I/O write cycle is used to

place a value into CONFIG_ADDRESS that specifies the PCI bus, the device on that bus, the

function within the device, and a specific configuration register of the device function being

accessed. CONFIG_ADDRESS31 must be 1 to enable a configuration cycle. CONFIG_DATA then

becomes a window into the four bytes of configuration space specified by the contents of

CONFIG_ADDRESS. Any read or write to CONFIG_DATA results in the MCH translating the

CONFIG_ADDRESS into the appropriate configuration cycle.

The MCH is responsible for translating and routing the processor’s I/O accesses to the

CONFIG_ADDRESS and CONFIG_DATA registers to internal MCH configuration registers for

HI_A, HI_B.

3.3 General Routing Configuration Accesses

The MCH supports two Hub interfaces: HI_A and HI_B. PCI configuration cycles are selectively

routed to one of these interfaces. The MCH is responsible for routing PCI configuration cycles to

the proper interface. PCI configuration cycles to ICH4 internal devices and Primary PCI (including

downstream devices) are routed to the ICH4 via HI_A. PCI configuration cycles to any of the

16-bit hub interfaces are routed to HI_B. AGP configuration cycles are routed to AGP. The AGP

interface is treated as a separate PCI bus from the configuration point of view. Routing of

configuration accesses to HI_B is controlled via the standard PCI-to-PCI bridge mechanism using

information contained within the primary bus number, the secondary bus number, and the

subordinate bus number registers of the corresponding PCI-to-PCI bridge device.

Note: The MCH supports a variety of connectivity options. When any of the MCH’s interfaces are

disabled, the associated interface’s device registers are not visible. Configuration cycles to these

registers will return all 1s for a read and master abort for a write.