Hub Datasheet

1
Working page only. Do not distribute.
1-1 Supported Memory Modes ..........................................................................................18
1-2 DIMM Support............................................................................................................18
2-1 Host Interface Signals..................................................................................................23
2-2 DDR Channel A Signals..............................................................................................26
2-3 DDR Channel B Signals..............................................................................................29
2-4 Hub Interface_A Signals .............................................................................................32
2-5 Hub Interface_B Signals..............................................................................................32
2-6 AGP Arbitration Signals..............................................................................................33
2-7 AGP Address/ Data Signals.........................................................................................34
2-8 AGP Command/ Control Signals ................................................................................35
2-9 Clocks, Reset, and Miscellaneous Signals ..................................................................37
3-1 MCH Logical Configuration Resources......................................................................40
3-2 Chipset Host Controller Register Address Map (D0:F0) ............................................45
3-3 PAM Associated Attribute Bits ...................................................................................57
3-4 Chipset Host RAS Controller Register Address Map (D0:F1) ...................................79
3-5 PCI-to-AGP Bridge Register Address Map (D1:F0)...................................................98
3-6 Hub Interface_B PCI-to-PCI Register Map (D2:F0).................................................122
3-7 Hub Interface_B – PCI-to-PCI Bridge Error Reporting Register Address Map (D2:F1)
134
4-1 SMM Address Range ................................................................................................153
5-1 Key Differences Between AGP 3.0 and AGP 2.0 Signaling Modes.........................159
5-2 AGP 3.0 Downshift Mode Parameters ......................................................................160
5-3 AGP 3.0 and AGP 2.0 Support Command Types .....................................................161
5-4 AGP Summary of Transaction Coherency................................................................161
5-5 Data Rates and Signaling Levels Supported by the MCH ........................................162
5-6 DRAM Terminology .................................................................................................165
5-7 Supported System Bus and Memory Interface Configurations.................................166
5-8 Maximum Supported Memory Configurations .........................................................167
5-9 Memory per DIMM at Each DRAM Density............................................................167
5-10 Clock Connections.....................................................................................................168
5-11 ACPI State to Clock State Mapping..........................................................................171
6-1 Absolute Maximum Ratings......................................................................................173
6-2 DC Characteristics Functional Operating Range ......................................................173
6-3 Signal Groups System Bus Interface .........................................................................175
6-4 Signal Groups DDR Interface ...................................................................................175
6-5 Signal Groups AGP Interface....................................................................................176
6-6 Signal Groups Hub Interface 2.0 (HI_B) ..................................................................176
6-7 Signal Groups Hub Interface 1.5 (HI_A) ..................................................................176
6-8 Signal Groups Reset and Miscellaneous ...................................................................176
6-9 Operating Condition Supply Voltage ........................................................................177
6-10 System Bus Interface DC Characteristics..................................................................177
6-11 DDR Interface DC Characteristics ............................................................................178
6-12 AGP Interface DC Characteristics.............................................................................179
6-13 Hub Interface 2.0 (HI_B) with Parallel Buffer Mode Configured for 50 W.............179
6-14 Hub Interface 1.5 (HI_A) with Parallel Buffer Mode Configured for 50 Ω .............180
7-1 MCH Ball List by Signal Name ................................................................................186
7-2 MCH Ball List by Ball Number ................................................................................195
7-3 MCH LPKG Data for the System Bus ......................................................................207
7-4 MCH LPKG Data for DDR Channel A.....................................................................209
7-5 MCH LPKG Data for DDR Channel B.....................................................................211
7-6 MCH LPKG Data for Hub Interface_A ....................................................................213